SCM69C433TQ15 データシートの表示（PDF） - Motorola => Freescale

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SCM69C433TQ15

16K x 64 CAM

Motorola => Freescale 

Freescale Semiconductor, Inc.

FUNCTIONAL DESCRIPTION

the initialization operation is run if required. Normal matching

The MCM69C433 is a flexible content–addressable

memory (CAM) that can contain 16K entries of 64 bits each.

The widths of the match field and the output field are pro-

grammable, and the match time is designed to be 240 ns. As

a result, the MCM69C433 is well suited for datacom

applications such as Virtual Path Identifier/Virtual Circuit

Identifier (VPI/VCI) translation in ATM switches up to OC12

operations can then begin. A delete operation is provided to

remove stale data from the CAM table.

Several error codes are defined in the details of the

instruction set. When an error occurs, its corresponding code

is written into the error register and the error bit in the flag

register is set. The error bit is cleared and the error register is

set to FFFF16 by the next write to the operation register.

(622 Mbps) data rates and Media Access Control (MAC) ad-

dress lookup in Ethernet/Fast Ethernet bridges. The match

PROGRAMMING MODEL

duty cycle of the MCM69C433 is determined by the user,

Three types of registers are accessible through the

with a trade–off between the match request rate and the rate

MCM69C433’s control port: I/O registers, an operation reg-

of entries added to/deleted from the CAM. With the minimum

C. required 60 ns of idle time between matches, a typical value

IN of 370 insertions or deletions per second can be made. See

R, Figure 3 for a graph of the relationship between insertion/

TO deletion pairs and match duty cycle.

C In its basic operating mode, the MCM69C433 reads a data

DU input word through MQ bus and compares it to all the entries

ON in its CAM table. The MC pin is always asserted after the

IC comparisons have been made. If a match is found, the MS

EM pin is asserted, and the data associated with the matching

S entry is output on the MQ bus. If no match is found, the MQ

LE bus remains in a high–impedance state to facilitate depth ex-

CA pansion via the cascading of multiple CAMs.

ES Before the basic operating mode can be entered, several

RE start–up functions must be performed. First, the output width

F and match width must be designated by setting the

BY global–mask register. Second, a choice must be made

ED between buffered–entry mode and fast–entry mode. Next,

IV the 64–bit match/output data pairs must be loaded into the

CH table. Depending on the entry mode of choice, the table may

AR have to be initialized. Optionally, the “almost full” point may

ister, and result/condition code registers. Each register is

16 bits in length.

REGISTER NAME

I/O REGISTER 0

BIT NUMBER

15

I/O REGISTER 1

I/O REGISTER 2

I/O REGISTER 3

OPERATION REGISTER

FLAG REGISTER

ERROR CODE REGISTER

INTERRUPT REGISTER

ADDRESS

OFFSET

0

0

1

2

3

4

5

6

7

be set to provide warning of impending table overflow.

The input bits to be compared are defined by the global–

mask register. The mask bits that are 0 correspond to the bits

FLAG BIT DEFINITIONS

that are used in the match operation.Typically, the bits that

are used in matching are the high order bits in the 64–bit

CAM table entries, and the bits that are used as outputs are

the low order bits. While any of the bits can be defined as

match bits, the low order 32 bits of an entry are always driven

on the MQ bus as output data.

The choice of entry mode is a trade–off between speed of

entry and latency before matching operations can begin. In a

typical application, the fast–entry mode will be used to load

the initial values into the CAM table. Subsequently, the

initialize–table operation, which takes 120 ms, must be

executed to establish the required linkages and relationships

among the entries. After match operations have begun, the

buffered–entry mode should be used to enter new values

dynamically; even one addition in fast–entry mode will dis-

Bit 0: 1 = At least one interrupt enabled,

0 = No interrupts enabled

Bit 1: 1 = Last control port match successful,

0 = Last match unsuccessful

Bit 2: 1 = Table initialized, 0 = Table not initialized

Bit 3: 1 = Buffered–entry mode, 0 = Fast–entry mode

Bit 4: 1 = Entry queue empty,

0 = Entry queue not empty

Bit 5: 1 = Entry queue full, 0 = Entry queue not full

Bit 6: 1 = CAM table full, 0 = CAM table not full

Bit 7: 1 = Error condition set, 0 = No error

Bit 8: 1 = Table almost full, 0 = Table not almost full

Bit 9: 1 = ATM mode, 0 = Standard mode

Bit 10: 1 = Last operation complete, 0 = Not yet complete

able matching until the table is reinitialized. Table insertions

using the buffered–entry mode and the fast–entry mode

ERROR CODES

actually take the same amount of time unless the entry

FFFF No error

queue is full. The capacity of the queue is 14 entries.

FFFD Invalid instruction

After the entry mode choice is made, the table can be

FFFC Queue not empty for read

loaded. Each 64–bit entry is constructed by writing a 16–bit

FFFB Table not initialized

value to each of the four I/O registers in the control port of the

FFFA Queue not empty for write

MCM69C433. The insertion can then be processed. After all

FFF9 CAM table full

the start–up entries have been loaded into the CAM table,

FFF8 Entry queue full

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM69C433•SCM69C433

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