SCM69C433TQ15 データシートの表示（PDF） - Motorola => Freescale

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SCM69C433TQ15

16K x 64 CAM

Motorola => Freescale 

Freescale Semiconductor, Inc.

match bit as defined by the mask register is ignored for this

operation. The operation of the MCM69C433 guarantees

that no more than one matching entry can exist in the table,

unless they were accidently loaded using fast–entry mode.

This must be avoided by the user, as the results of subse-

quent matches and deletes will be undefined.

interrupt is generated if enabled by bit 4 of the interrupt

register.

If this mode is used to enter data, the initialize–table opera-

tion must be executed before matching operations can

begin. The entry–mode bit and the table–initialized bit of the

flag register are cleared by this operation.

Example: I/O Register 0 =

302016

I/O Register 1 =

000016

I/O Register 2 =

543A16

I/O Register 3 =

FE5516

Concatenated value = FE55543A0000302016

Global–Mask Register = C0000000FFFFFFFF16

BUFFERED–ENTRY MODE

This instruction is used to enter the buffered–entry mode.

When the MCM69C433 is in this mode, insert–value and

delete–value operations utilize the entry queue. This mode

can be entered at any time. Table entries are available for

Of the high–order 32 bits, the rightmost 30 bits

C. are cared by the global–mask register. Therefore,

IN the MCM69C433 will delete an entry, if it exists,

R, which has a value of 3E55543A16 in bits 61 – 32.

CTO CHECK FOR VALUE

NDU This instruction checks for a matching value in the CAM

ICO table via the control port. The contents of I/O registers 0 – 3

M are concatenated, with bit 15 of register 3 as the most signifi-

SE cant bit, and bit 0 of register 0 as the least significant bit. The

E bits that have a 0 in the corresponding bit of the global–mask

AL register are used to find a matching entry in the CAM table. If

SC such an entry is found, the last–match–successful bit of the

EE flag register is set. In addition, the matching entry is written to

FR I/O registers 0 – 3, with bit 15 of register 3 as the most signifi-

Y cant bit, and bit 0 of register 0 as the least significant bit

B If no match is found, the last–match–successful bit is

ED cleared. An interrupt is generated regardless of the result, if

HIV enabled by bit 2 of the interrupt register, when the operation

C has been completed. The operation of the MCM69C433

AR guarantees that no more than one matching entry can exist

match operations immediately, without running the initialize–

table operation, if all entries are made in this mode. Note that

if both the buffered–entry and fast–entry modes have been

used to input data, none of the entries are available for

matching until the initialize–table operation is executed. Con-

flicting table and queue values are resolved in favor of the

latest entry in the queue. For example, if there is an entry in

the CAM, a corresponding delete–entry in the queue, and a

later insert–entry in the queue (all with the same match data),

the queued insert–entry will return a match value.

RETURN ENTRY COUNT

This operation is used to determine the number of valid en-

tries in the MCM69C433. The value is returned in I/O register

0, and reflects the sum of the number of valid entries in the

CAM table and the inserts in the entry queue.

SET GLOBAL–MASK REGISTER

This operation is used to indicate the bits to be used in per-

forming matches. A 1 indicates that a bit should be ignored in

the match operation, while a 0 indicates that a bit should be

in the table. If uninterrupted by match port activity, the check

used in the match operation.

for value instruction will finish in 16 clock cycles. NOTE: If

When this operation is executed, the contents of I/O regis-

both the control and matching ports are utilized simulta-

ters 0 – 3 are concatenated, with bit 15 of register 3 as the

neously, see the Simultaneous Port Operations section.

most significant bit, and bit 0 of register 0 as the least signifi-

INITIALIZE TABLE

cant bit. The resulting 64–bit value is written to the global–

mask register.

If fast–entry mode has been used to load the CAM table,

This operation should be executed before entering re-

the initialize–table operation must be used to establish the

quired values into the CAM table. Otherwise, the initialize–

needed relationships and linkages between the entries in the

table instruction must be executed if the global–mask

table before matching can proceed. Upon completion, this

register is changed after data is loaded into the CAM.

operation sets the table–initialized bit in the flag register, and

generates an interrupt if enabled by bit 3 of the interrupt reg-

SET ALMOST–FULL POINT

ister. It also sets the buffered–entry mode bit in the flag regis-

ter. This operation makes the programming model’s registers

read–only for up to 120 ms after the acknowledgment of the

op code write cycle.

This operation is used to define the “almost–full” condition

in the CAM table. The 14 low–order bits of I/O register 0 are

copied to the almost–full–point register. If an entry is added

to the MCM69C433 (via the insert–value operation) that

FAST–ENTRY MODE

causes the valid–entry count to equal the almost–full point,

then bit 8 of the flag register is set, and an interrupt is gener-

This instruction is used to enter the fast–entry mode.

ated if enabled by bit 5 of the interrupt register. The value of

When the MCM69C433 is in this mode, insert–value opera-

the almost–full register can be changed dynamically during

tions bypass the entry queue and write new table entries

match operations. For example, it could first be set to 8192 to

directly to the CAM table. The fast–entry mode can only be

generate an interrupt when the table is half full. When that

entered while the entry queue is empty, as reflected by the

point is reached, the register could be reprogrammed to

queue–empty flag being set (bit 4 of the flag register.) If this

12,288 to provide warning that the table has become three–

operation is attempted while the entry queue is not empty,

quarters full. The almost–full interrupt is generated, if

the value FFFA16 is written to the error code register, the

error–condition flag (bit 7) is set in the flag register, and an

enabled, based on the number of entries in the CAM table.

Entries in the queue are not included in the count.

MOTOROLA FAST SRAM

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