ADSP-2104 データシートの表示（PDF） - Analog Devices
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ADSP-2104 Datasheet PDF : 36 Pages
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ADSP-2104/ADSP-2109
Program Memory Maps
Program memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.
INTERNAL RAM
512 WORDS
LOADED FROM
EXTERNAL
BOOT MEMORY
RESERVED
1.5K
0x0000
0x01FF
0x0200
0x0000
EXTERNAL
14K
0x07FF
0x0800
0x37FF
0x3800
EXTERNAL
14K
INTERNAL RAM
512 WORDS
RESERVED
1.5K
0x39FF
0x3A00
MMAP=0
0x3FFF
MMAP=1
No Booting
0x3FFF
Figure 4. ADSP-2104 Program Memory Maps
4K
INTERNAL
ROM
0x0000
RESERVED
0x0FF0
0x0FFF
0x1000
2K
EXTERNAL
2K
INTERNAL
ROM
RESERVED
0x0000
0x07FF
0x0800
0x0FF0
0x0FFF
0x1000
12K
EXTERNAL
MMAP=0
0x3FFF
10K
EXTERNAL
2K
INTERNAL
ROM
MMAP=1
0x37FF
0x3800
0x3FFF
Figure 5. ADSP-2109 Program Memory Maps
ADSP-2104
When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when RESET is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 512 words between addresses 0x3800–0x39FF. In
this configuration, program memory is not booted although it
can be written to and read under program control.
Data Memory Interface
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-2104/ADSP-2109 processors support memory-
mapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.
Data Memory Map
ADSP-2104
On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
1K EXTERNAL
DWAIT0
1K EXTERNAL
DWAIT1
0x0000
0x0400
0x0800
10K EXTERNAL
DWAIT2
EXTERNAL
RAM
1K EXTERNAL
DWAIT3
1K EXTERNAL
DWAIT4
256 WORDS
MEMORY-MAPPED
CONTROL REGISTERS
& RESERVED
0x3000
0x3400
0x3800
0x3900
INTERNAL
0x3C00
RAM
0x3FFF
Figure 6. Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.
REV. 0
–7–
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