LTC1668IG データシートの表示（PDF） - Linear Technology

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LTC1668IG

12-Bit, 14-Bit, 16-Bit, 50Msps DACs

Linear Technology 

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

LTC1666/LTC1667/LTC1668

RIOUT B

1.1k

LADCOM

18

RIOUT A

1.1k

IOUT A

20

IOUT B

19

52.3Ω

52.3Ω

5pF

5pF

VSS

23

– 5V

1666/7/8 F04

Figure 3. Equivalent Analog Output Circuit

LADCOM

The LADCOM pin is the common connection for the

internal DAC attenuator ladder. It usually is tied to analog

ground, but more generally it should connect to the same

potential as the load resistors on IOUT A and IOUT B. The

LADCOM pin carries a constant current to VSS of approxi-

mately 0.32 • (IOUTFS), plus any current that flows from

IOUT A and IOUT B through the RIOUT A and RIOUT B resistors.

Output Compliance

The specified output compliance voltage range is ±1V. The

DC linearity specifications, INL and DNL, are trimmed and

guaranteed on IOUT A into the virtual ground of an

I-to-V converter, but are typically very good over the full

output compliance range. Above 1V the output current will

start to increase as the DAC current steering switch

impedance decreases, degrading both DC and AC linear-

ity. Below –1V, the DAC switches will start to approach the

transition from saturation to linear region. This will de-

grade AC performance first, due to nonlinear capacitance

and increased glitch impulse. AC distortion performance

is optimal at amplitudes less than ±0.5VP-P on IOUT A and

IOUT B due to nonlinear capacitance and other large-signal

effects. At first glance, it may seem counter-intuitive to

decrease the signal amplitude when trying to optimize

SFDR. However, the error sources that affect AC perfor-

mance generally behave as additive currents, so decreas-

ing the load impedance to reduce signal voltage amplitude

will reduce most spurious signals by the same amount.

5V

0.1µF

0.1µF

C1

0.1µF

RSET

2k

C2

0.1µF

REFOUT

2.5V

VDD

REFERENCE

IREFIN

LTC1668

COMP1

COMP2

VSS

IOUT A

+

16-BIT

HIGH SPEED

–

DAC

IOUT B

LADCOM

AGND DGND CLK DB15 DB0

110Ω

50Ω 50Ω

0.1µF

– 5V

16

DIGITAL

DATA

CLK

IN

OUT 1 OUT 2

HP8110A DUAL

PULSE GENERATOR

CLK

IN

HP1663EA

LOGIC ANALYZER WITH

PATTERN GENERATOR

1666/7/8 F05

LOW JITTER

CLOCK SOURCE

Figure 4. AC Characterization Setup (LTC1668)

MINI-CIRCUITS

T1–1T

TO HP3589A

SPECTRUM

ANALYZER

50Ω INPUT

13

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