LTC1668IG データシートの表示（PDF） - Linear Technology

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LTC1668IG

12-Bit, 14-Bit, 16-Bit, 50Msps DACs

Linear Technology 

LTC1666/LTC1667/LTC1668

APPLICATIO S I FOR ATIO

Resistor Loaded Outputs

A differential resistor loaded output configuration is shown

in Figure 6. It is simple and economical, but it can drive

only differential loads with impedance levels and ampli-

tudes appropriate for the DAC outputs.

The recommended single-ended resistor loaded configu-

ration is essentially the same circuit as the differential

resistor loaded, case—simply use the IOUT A output,

referred to ground. Rather than tying the unused IOUT B

output to ground, it is preferred to load it with the equiva-

lent RLOAD of IOUT A. Then IOUT B will still swing with a

waveform complementary to IOUT A.

52.3Ω 52.3Ω

IOUT A

LTC1666/

LTC1667/

LTC1668

IOUT B

1666/7/8 F07

Figure 6. Differential Resistor-Loaded Output

Op Amp I to V Converter Outputs

Adding an op amp differential to single-ended converter

circuit to the differential resistor loaded output gives the

circuit of Figure 7.

This circuit complements the capabilities of the trans-

former-coupled application at lower frequencies, since

available op amps can deliver good AC distortion perfor-

mance at signal frequencies of a few MHz down to DC. The

optional capacitor adds a single real pole of filtering, and

helps reduce distortion by limiting the high frequency

signal amplitude at the op amp inputs. The circuit swings

±1V around ground.

Figure 8 shows a simplified circuit for a single-ended

output using I-to-V converter to produce a unipolar

buffered voltage output. This configuration typically has

the best DC linearity performance, but its AC distortion at

higher frequencies is limited by U1’s slewing capabilities.

Digital Interface

The LTC1666/LTC1667/LTC1668 have parallel inputs that

are latched on the rising edge of the clock input. They

accept CMOS levels from either 5V or 3.3V logic and can

accept clock rates of up to 50MHz.

Referring to the Timing Diagram and Block Diagram, the

data inputs go to master-slave latches that update on the

rising edge of the clock. The input logic thresholds, VIH =

2.4V min, VIL = 0.8V max, work with 3.3V or 5V CMOS

levels over temperature. The guaranteed setup time, tDS,

is 8ns minimum and the hold time, tDH, is 4ns minimum.

The minimum clock high and low times are guaranteed at

6ns and 8ns, respectively. These specifications allow the

LTC1666/LTC1667/LTC1668 to be clocked at up to 50Msps

minimum.

For best AC performance, the data and clock waveforms

need to be clean and free of undershoot and overshoot.

Clock and data interconnect lines should be twisted pair,

coax or microstrip, and proper line termination is impor-

tant. If the digital input signals to the DAC are considered

as analog AC voltage signals, they are rich in spectral

components over a broad frequency range, usually in-

COUT

500Ω

IOUT A

LTC1666/

LTC1667/

LTC1668

IOUT B

60pF

52.3Ω

200Ω

200Ω

–

LT1809

+

VOUT

±1V

10dBm

52.3Ω

500Ω

1666/7/8 F08

Figure 7. Differential to Single-Ended Op Amp I-V Converter

IOUT A

LTC1666/

LTC1667/

LTC1668

IOUT B

LADCOM

IOUTFS

10mA

200Ω

RFB

200Ω

–

U1

+LT®1812

VOUT

0V TO 2V

1666/7/8 F09

Figure 8. Single-Ended Op Amp I to V Converter

15

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