ST7063C データシートの表示（PDF） - Sitronix Technology Co., Ltd.
部品番号
コンポーネント説明
メーカー
ST7063C Datasheet PDF : 12 Pages
| |||
ST7063C
n Functional Description
Clock
The CL1 is the clock to latch data on the falling edge. It latches the data input from
the bi-directional shift register at the falling edge of CL1 and transfers its outputs to
the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts
the serial data at the falling of CL2 and transfers the output of each bit of the register
to the latch circuit.
Shift Registers And Data I/O
The ST7063C supplies two sets of 40-bit shift register, which controls the shift
direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2
controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift
direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction
changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is
from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from
S41 to S80.
The DL1, DR1, DL2, DR2 are data input or output option function.
SHL1
0
1
SHL2
0
1
Shift Direction of Channel 1
Shift Direction
DL1
S1 à S40
IN
S40 à S1
OUT
DR1
OUT
IN
Shift Direction of Channel 2
Shift Direction
DL2
S41 à S80
IN
S80 à S41
OUT
DR2
OUT
IN
V1.3b
9/12
2005/11/08
Share Link: 