STK1744-D35I データシートの表示（PDF） - Unspecified
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STK1744-D35I Datasheet PDF : 12 Pages
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STK1744
DEVICE OPERATION
The STK1744 is a 32K x 8 nonvolatile static RAM
with a full-function real-time clock (RTC). Nonvolatile
data is preserved in integral QuantumTrap Nonvol-
atile Elements and is not subject to battery failure or
capacitor discharge. The real-time clock registers
reside in the eight uppermost RAM locations, and
contain century, year, month, date, day, hour, minute
and second data in 24-hour BCD format. Corrections
for the day of the month and leap years are made
automatically. This nonvolatile time-keeping RAM is
functionally similar to any JEDEC standard 32K x 8
SRAM.
The RTC registers are double-buffered to avoid
access of incorrect data that could otherwise occur
during clock update cycles. The double-buffered
system prevents time loss by maintaining internal
clock operation while time register data is accessed.
The STK1744 contains integral power-fail circuitry
that deselects the device when VCC drops below
VSWITCH.
The STK1744 is a pin-compatible replacement for
the ST Microelectronics M48T35 and the Dallas
Semiconductor DS1744, but without the limitations
of an embedded lithium battery. The Simtek module
uses a double-layer high-value capacitor to maintain
RTC operation on every power down for at least 30
days. The part can be soldered directly onto printed
circuit boards and handled without concern for dam-
aging or discharging internal batteries. Unlike some
other RTCs, the STK1744 is Year 2000-compliant.
NOISE CONSIDERATIONS
Note that the STK1744 is a high-speed memory and
so must have a high-frequency bypass capacitor of
approximately 0.1µF connected between VCC and
VSS, using leads and traces that are as short as pos-
sible. As with all high-speed CMOS ICs, normal care-
ful routing of power, ground and signals will help
prevent noise problems.
SRAM AND RTC READ
The STK1744 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,760 data
bytes or 8 RTC registers will be accessed. When the
READ is initiated by an address transition, the out-
puts will be valid after a delay of tAVQV (READ cycle
#1). If the READ is initiated by E or G, the outputs will
be valid at tELQV or at tGLQV, whichever is later (READ
cycle #2). The data outputs will repeatedly respond to
address changes within the tAVQV access time without
the need for transitions on any control input pins, and
will remain valid until another address change or until
E or G is brought high or W is brought low.
Note that the eight most significant bytes of the
address space are reserved for accessing the RTC
registers, as shown in the RTC Register Map.
While the double-buffered RTC register structure
reduces the chance of reading incorrect data from the
clock, the user should halt internal updates to the
RTC REGISTER MAP
ADDRESS
BCD DATA
(HEXADECIMAL)
D7
D6
D5
D4
D3
7FF8
W
R
10 Centuries
7FF9
X
10 Seconds
7FFA
X
10 Minutes
7FFB
X
X
10 Hours
7FFC
1
FT
X
X
X
7FFD
X
X
10 Dates
7FFE
X
X
X
10 Mos.
7FFF
10 Years
Key:
R = Read Bit
W = Write Bit
1 = Battery Flag high (there is no battery to fail)
FT = Frequency test bit
X = Don’t Care
D2
D1
Centuries
Seconds
Minutes
Hours
Days
Dates
Months
Years
FUNCTION/RANGE
D0
Centuries: 00 - 39, Control
Seconds: 00 - 59
Minutes: 00 - 59
Hours: 00 - 23
Days: 01 - 07
Dates: 01 - 31
Months: 01 - 12
Years: 00 - 99
January 2003
7 Document Control # ML0020 rev 0.0
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