SX20AD-I データシートの表示（PDF） - Unspecified

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SX20AD-I

Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug

Unspecified 

SX18AC/SX20AC/SX28AC/SX18AC75/SX20AC75/SX28AC75

1.2 Key Features

50 MIPS Performance

• SX18AC/SX20AC/SX28AC: DC - 50 MHz operation

SX18AC75/SX20AC75/SX28AC75: DC - 75 MHz

• SX18AC/SX20AC/SX28AC: 20 ns instruction cycle,

60 ns internal interrupt response

SX18AC75/SX20AC75/SX28AC75: 13.3 ns instruction

cycle, 39.9 ns internal interrupt response

• 1 instruction per clock (branches 3)

Hardware Peripheral Features

• One 8-bit Real Time Clock/Counter (RTCC) with pro-

gramable 8-bit prescaler

• Watchdog Timer (shares the RTCC prescaler)

• Analog comparator

• Brown-out detector

• Multi-Input Wakeup logic on 8 pins

• Internal RC oscillator with configurable rate from 31.25

kHz to 4 MHz

• Power-On-Reset

EE/FLASH Program Memory and SRAM Data Memory

• Access time of < 10 ns provides single cycle access

• EE/Flash rated for > 10,000 rewrite cycles

• 2048 Words EE/Flash program memory

• 136x8 bits SRAM data memory

CPU Features

• Compact instruction set

• All instructions are single cycle except branch

• Eight-level push/pop hardware stack for subroutine

linkage

• Fast table lookup capability through run-time readable

code (IREAD instruction)

• Totally predictable program execution flow for hard

real-time applications

Packages

• 18-pin SOP/DIP, 20-pin SSOP, 28-pin SOP/DIP/SSOP

Programming and Debugging Support

• On- chip in-system programming support with serial

and parallel interfaces

• In-system serial programming via oscillator pins

• On-chip in-System debugging support logic

• Real-time emulation, full program debug, and integrat-

ed development environment offered by third party tool

vendors

Fast and Deterministic Interrupt

• Jitter-free 3-cycle internal interrupt response

• Hardware context save/restore of key resources such

as PC, W, STATUS, and FSR within the 3-cycle inter-

rupt response time

• External wakeup/interrupt capability on Port B (8 pins)

Flexible I/O

• All pins individually programmable as I/O

• Inputs are TTL or CMOS level selectable

• All pins have selectable internal pull-ups

• Selectable Schmitt Trigger inputs on Ports B, and C

• All outputs capable of sourcing/sinking 30 mA

• Port A outputs have symmetrical drive

• Analog comparator support on Port B (RB0 OUT, RB1

IN-, RB2 IN+)

• Selectable I/O operation synchronous to the oscillator

clock

© 2000 Scenix Semiconductor, Inc. All rights reserved.

-3-

www.scenix.com

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