TDA8003TS/C1 データシートの表示（PDF） - Philips Electronics

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TDA8003TS/C1

I2C-bus SIM card interface

Philips Electronics 

Philips Semiconductors

I2C-bus SIM card interface

Product specification

TDA8003TS

Clock circuit

The clock to the card is either derived from pin SIMCLK

(2 to 20 MHz) or from the internal oscillator.

During a card session, fCLK may be chosen to be

1⁄2fSIMCLK or 1⁄4fSIMCLK depending on bit DT/DFN.

For the card Sleep mode, CLK may be chosen stop LOW,

stop HIGH or 1⁄2fosc (1.25 MHz) with bits CLKPD1 and

CLKPD2. This predefined value will be applied to CLK

when bit PDOWN is set to logic 1.

The first CLK pulse has the correct width, and all frequency

changes are synchronous, ensuring that no pulse is

smaller than 45% of the shortest period.

The duty cycle is within 45 and 55% in stable state, the rise

and fall times are less than 8% of the period and

precaution has been taken so that there is no overshoot or

undershoot.

Activation sequence

Figure 4 shows the activation sequence. When the card is

inactive, VCC, CLK, RST and I/O are LOW, with

low-impedance with respect to ground. The DC-to-DC

converter is stopped. SIMI/O is pulled HIGH at VDDI via the

20 kΩ pull-up resistor. When all conditions are met (supply

voltage, card present, no hardware problems), the

microcontroller may initiate an activation sequence by

setting bit START to logic 1 (t0) via the I2C-bus:

1. The DC-to-DC converter is started (t1).

2. VCC starts rising from 0 to 3 or to 5 V according to

3 V/5 VN control bit with a controlled rise time of

0.17 V/µs typically (t2).

3. I/O buffer is enabled in reception mode (t3).

4. CLK is sent to the card reader with RST = LOW, and

the count of 45000 (44745 for C2) CLK pulses is

started (t4 = tact).

5. If a start bit is detected on I/O, the clock counter is

stopped with RST = LOW. If not, RST = HIGH, and a

new count of 45000 (44745 for C2) CLK pulses is

started (t5).

If a start bit is detected on I/O and the clock counter is

stopped with RST = HIGH, the card session may continue.

If not, bit MUTE is set in the status register and SIMERR is

pulled LOW. The microcontroller may initiate a

deactivation sequence by setting bit START to logic 0.

If a start bit is detected during the 200 first CLK pulses of

each count slot, then it will not be taken into account. If a

start bit is detected during 200 and 352 CLK pulses of

each slot, then bit EARLY is set in the status register and

SIMERR is pulled LOW. The microcontroller may initiate a

deactivation sequence by setting bit START to logic 0.

The sequencer is clocked by 1⁄64fosc which leads to a time

interval T of 25 µs typically. Thus t1 = 0 to 1⁄64T;

t2 = t1 + 3⁄2T; t3 = t1 + 7⁄2T; t4 = t1 + 4T and t5 depends on

the SIMCLK frequency.

Deactivation sequence

Figure 5 shows the deactivation sequence. When the

session is completed, the microcontroller sets bit START

to logic 0. The circuit will execute an automatic

deactivation sequence:

1. Card reset, RST falls to LOW (t10).

2. CLK is stopped (t11).

3. I/O falls to LOW (t12).

4. VCC falls to 0 V with typically 0.17 V/µs slew rate (t13).

The deactivation is completed when VCC reaches

0.4 V (tde).

5. The DC-to-DC converter is stopped and CLK, RST,

VCC and I/O become low-impedance with respect to

PGND (t14).

Where t10 < 1⁄64T; t11 = t10 + 1⁄2T; t12 = t10 + T;

t13 = t12 + 5 µs and t14 = t10 + 4T.

2000 Apr 20

10

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