QT60040-D データシートの表示（PDF） - Quantum Research Group
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QT60040-D Datasheet PDF : 10 Pages
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©Quantum Research Group Ltd.
Figure 2-1 Basic Circuit Diagram
+5
1
Vdd
3
Opt1
X1 2
4
Opt2
X2 13
X3 12
5 Q1
X4 11
6 Q2
7 Q3
Y 10
8 Q4
Cs 9
Vss
14
M1
M2
M3
M4
Cs
2 - CIRCUIT SPECIFICS
The basic QT60040 circuit is shown in Figure 2-1.
2.1 CS CAPACITOR
The QT60040 requires only a single external sampling capacitor
(Cs) to operate. This capacitor should have good stability
characteristics. It is possible but not optimal to use an X7R type
capacitor, but for best stability a plastic type such as polyester or
PPS film should be used. Increasing values will result in
increased sensitivity, but too much sensitivity can also result in
spurious operation. The optimal value of Cs will depend on the
type of panel material, its thickness, and key geometry;
experimentation is required to determine the proper value.
Typical suitable values of Cs range from 22nF to 220nF; 47nF is
a good value to start from in most cases.
2.2 OPTION PINS
There are two option pins whose function is shown in Table 2-1.
OPT1 is used to set the rollover option. If this pin is connected to
ground, the IC will only sense one key at a time. If OPT1 is left
open or connected to Vdd, the IC can sense any two keys
simultaneously and will suppress additional keys.
OPT2 is used to set the calibration time-out function. If OPT2 is
connected to ground, keys will time out and recalibrate after 10
seconds of continuous detection on a key. If OPT2 is left open or
connected to Vdd, keys will recalibrate after 60 seconds. In either
case the keys will continue to be functional after the time-out, to
increased amounts of finger touch.
2.3 POWER SUPPLY
The IC uses the power supply rail as an internal reference
voltage. If the power supply is shared with another electronic
system, care should be taken to assure that the supply is free of
digital spikes, sags, and surges which can adversely affect the
circuit. The QT60040 will track slow changes in Vcc, but it can be
adversely affected by rapid voltage steps and impulse noise on
the supply rail.
The power supply can range from +2.5 to +5.5 volts, and should
be regulated via a standard regulator such as a 78L05 type. In
cases where low cost is an objective, it is possible to use
double-zener regulation.
For proper operation a 100nF (0.1uF) ceramic bypass capacitor
should be used between Vdd and Vss; the bypass cap should be
placed very close to the device’s power pins.
2.4 OUTPUTS
The device has four active-high outputs, one per sensing
channel, which indicate touch. These outputs should be used for
logic-level switching only and should not drive loads of more than
1mA. High loads can cause shifts in device Vdd and Vss rails
which can lead to spurious operation.
2.5 ESD PROTECTION
In general the QT60040 will be protected from direct static
discharge by the overlying panel. However, even with a panel,
transients can still flow into the electrode via induction, or in
extreme cases, via dielectric breakdown. Porous or thin materials
may allow a spark to tunnel right through the panel material.
Testing is required to reveal any problems. The QT60040 does
have diode protection on its terminals which can absorb and
protect the device from most induced discharges, up to 20mA;
the usefulness of the internal clamping will depend on the
dielectric properties, panel thickness, rise time of the ESD
transients, and their duration.
The device pins can be further protected by inserting series
resistance into the X and Y lines. The resistances chosen should
not be so high as to interfere with the QT process. Every board
layout is different and thus it is difficult to specify a suitable value,
however, typical values will range from 1K ohms to 47K ohms. In
serious cases additional low-capacitance high-conductance
clamp diodes (e.g. BAV99) may be added to shunt ESD aside
from the X and Y pins to the power and ground rails.
The QT60040's 'X' drive lines are always being driven at low
impedance; they are never 3-state unless the circuit is just
powering up or is powered down. This is a considerable
advantage in dealing with ESD. The 4 output pins may also be
vulnerable and should be resistor and/or diode protected if they
are in danger of being subject to ESD.
OPT1
OPT2
Table 2-1 Option Pin Functions
Pin 3 Vdd
2 keys can be sensed
Vss
1 key only can be sensed
Pin 4 Vdd
60 seconds to recalibration
Vss
10 seconds to recalibration
lQ
-5-
QT60040 / R1.04 / 0303
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