AT91M40400(1998) データシートの表示（PDF） - Atmel Corporation
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AT91M40400 Datasheet PDF : 7 Pages
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EBI: External Bus Interface
The EBI generates the signals which control the access to
the external memory or peripheral devices. The EBI is fully
programmable and can address up to 64M bytes. It has
eight chip selects and a 24-bit address bus, the upper four
bits of which are multiplexed with a chip select.
The 16-bit data bus can be configured to interface with 8-
or 16-bit external devices. Separate read and write control
signals allow for direct memory and peripheral interfacing.
The EBI supports different access protocols allowing single
clock cycle memory accesses.
The main features are:
• External Memory Mapping
• Up to 8 chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
AIC: Advanced Interrupt Controller
The AT91 has an 8-level priority, individually maskable,
vectored interrupt controller. This feature substantially
reduces the software and real time overhead in handling
internal and external interrupts.
The interrupt controller is connected to the NFIQ (fast inter-
rupt request) and the NIRQ (standard interrupt request)
inputs of the ARM7TDMI processor. The processor’s NFIQ
line can only be asserted by the external fast interrupt
request input: FIQ. The NIRQ line can be asserted by the
interrupts generated by the on-chip peripherals and the
external interrupt request lines: IRQ0 to IRQ2.
An 8-level priority encoder allows the customer to define
the priority between the different NIRQ interrupt sources.
Internal sources are programmed to be level sensitive or
edge triggered. External sources can be programmed to be
positive or negative edge triggered or high or low level sen-
sitive.
PIO: Parallel I/O Controller
The AT91M40400 has 32 programmable I/O lines. Six pins
on the AT91M40400 are dedicated as general purpose I/O
pins (P16, P17, P18, P19, P23 and P24). Other I/O lines
are multiplexed with an external signal of a peripheral to
optimize the use of available package pins. The PIO con-
troller enables generation of an interrupt on input change
and insertion of a simple input glitch filter on any of the PIO
pins.
USART: Universal
Synchronous/Asynchronous
Receiver/Transmitter
The AT91 provides two identical, full-duplex, universal syn-
chronous/asynchronous receiver/transmitters that inter-
face to the APB and are connected to the Peripheral Data
Controller.
The main features are:
• Programmable Baud Rate Generator
• Parity, Framing and Overrun Error Detection
• Line Break Generation and Detection
• Automatic Echo, Local Loopback and Remote Loopback
channel modes
• Multi-drop Mode: Address Detection and Generation
• Interrupt Generation
• Two Dedicated Peripheral Data Controller channels
• 5-, 6-, 7- and 8-bit character length
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AT91M40400
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