TND301 データシートの表示（PDF） - ON Semiconductor
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TND301 Datasheet PDF : 8 Pages
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TND301
The Building Blocks
Clock Generator
The Clock Generator uses a Phase Locked Loop (PLL)
circuit to generate the Master Clock (see Figure 5). A Crystal
Oscillator Circuit generates a low phase noise signal that is
received by a phase detector. The phase detector compares the
phase of the crystal oscillator with the output of the Divide by
N counter. If both phases are the same, the circuit is in LOCK
and a small output pulse from the phase detector is averaged
by the Loop Filter. The Loop Filter outputs a voltage to the
VCO which defines the Master Clock frequency. The Divide
Crystal
Oscillator
Circuit
Phase
Detector
MC100EP40
MC100EP140
by N counter can be programmed to increase or decrease the
Master Clock frequency. The Master Clock is equal to the
Crystal Oscillator frequency times the value N. This is why a
PLL is sometimes called a frequency multiplier. The PLL is a
feedback circuit; if the Master Clock begins to drift away, the
shift in phase will be discovered by the Phase Detector The
Phase Detector will then generate a wider output pulse which
will be averaged by the Loop Filter and this new value will
push the VCO back in the right direction.
Loop Filter
VCO
Voltage Controlled
Oscillator
MC100EL1648
Master
Clock
Divide by N
MC100EP32
MC100EP33
MC100LVEP34
MC100EP139
MC100EP016
Control Input
Figure 5. Clock Generation Using Phase Locked Loop Circuit
NBC12429
NBC12430
1
Clock Distribution
Clock Distribution circuits receive a single differential
input and “fan out” multiple outputs with minimum skew
(see Figure 6).
2
1
N
1:2
MC100EL11
MC100LVEL11
MC100EP11
MC100LVEP11
Dual 1:3
MC100EL13
MC100LVEL13
1:4
MC100EL15
Figure 6. Clock Distribution Using 1:N
Clock Driver Circuit
1:5
MC100EL14
MC100LVEL14
MC100EP14
MC100LVEP14
Dual 1:5
MC100LVEP210
1:6
MC100E211
1:10
MC100LVEP111
1:15
MC100LVE222
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