TND301 データシートの表示（PDF） - ON Semiconductor
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TND301 Datasheet PDF : 8 Pages
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TND301
The Challenges: We Have a Better Solution
Clock Management systems require the clocks to have low
jitter and low skew. ECL logic provides less jitter and skew
with a higher operating frequency than other technologies.
ECL logic technology offers a number of advantages over
CMOS, LVDS, and TTL in reducing clock errors caused by
jitter and skew. ECL devices have 1 ps jitter and 25 ps skew
compared to 15 ps jitter and 100 ps skew for LVDS and CMOS
devices. (See Figure 11 and Figure 12). The frequency of ECL
logic is 3 Ghz maximum frequency compared to 300 Mhz
maximum frequency for LVDS and CMOS logic (see Figure
13). The rise and fall times of clock signals is very critical for
edge placement. ECL logic provides rise and fall times of 100
ps compared to rise and fall times of 800 ps for LVDS and
CMOS logic (see Figure 14).
ECL logic technologies offer a number of advantages for
reducing the noise due to crosstalk and signal mismatch on the
backplane over CMOS, LVDS, and TTL technologies. ECL
signals are differential signals and can be individually
terminated to match the transmission impedance of the
backplane ECL signals have adequate current (50 mA) to drive
a backplane and can deliver signals with maximum frequencies
of 3 Ghz. ECL peak–to–peak output signals of 800 mV provide
a good signal–to–noise ratio and excellent EMI characteristics.
25
20
CMOS
15
LVDS
10
5
0
2000
ECL
2001
2002
2003
Figure 11. Standard I/O rms Jitter
1000
100
10
CMOS
LVDS
ECL
1
2000
2001
2002
2003
Figure 12. Standard I/O Skew
45
40
35
30
25
ECL/PECL
20
15
10
5
0
2000
LVDS
CMOS
2001
2002
2003
Figure 13. Standard I/O Fmax
10000
1000
100
10
CMOS
LVDS
ECL
1
2000
2001
2002
2003
Figure 14. Standard Rise/Fall Time
Comparisons
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