USB1T11A(2008) データシートの表示（PDF） - Fairchild Semiconductor
部品番号
コンポーネント説明
メーカー
USB1T11A Datasheet PDF : 11 Pages
| |||
Pin Configuration
MODE 1
/OE 2
RCV 3
VP 4
VM 5
SUSPND 6
GND 7
14 VCC
13 VMO/FSEO
12 VPO
11 D+
10 D-
9 SPEED
8 NC
12
11
10
VPO 13
NC 14
VMO/FSEO 15
VCC 16
1
2
3
9
8 NC
7 GND
6
SUSPND
5
VM
4
Figure 2. TSSOP and SOIC Pin Assignments
Pin Descriptions
Figure 3. MLP Pin Assignments
Pin Names
RVC
/OE
Mode
VPO,VMO/FSEO
VP,VM
D+, D-
SUSPND
Speed
VCC
GND
I/O
O
I
I
I
O
AI/O
I
I
Description
Receive Data. CMOS level output for USB differential input.
Output Enable. Active LOW, enables the transceiver to transmit data on the bus.
When not active, the transceiver is in receive mode.
Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and, in this
GND, the VMO/FSEO pin takes the function of FSEO (force SEO).
Inputs to differential driver. (Outputs from SIE.)
Mode
0
VPO
VMO/FSEO
RESULT
0
Logic “0”
0
/SEO
1
Logic “1”
1
/SEO
1
0
0
/SEO
0
1
Logic “0”
1
0
Logic “1”
1
1
Illegal Code
Gated version of D- and D+. Outputs are logic “0” and logic “1.” Used to detect single
ended zero (/SEO), error conditions, and interconnected speed. (Input to SIE).
VP
VM
RESULT
0
0
/SEO
0
1
Low Speed
1
0
Full Speed
0
1
Error
Data+, Data-. Differential data bus conforming to the Universal Serial Bus standard.
Suspend. Enables a low-power state while the USB bus is inactive. While the
suspend pin is active, it drives the RCV pin to a logic “0” state. Both D+ and D- are 3-
STATE.
Edge Rate Control. Logic “1” operates at edge rates for “full speed.” Logic “0”
operates edge rates for “low speed.”
3.0 to 3.6 power supply.
Ground reference.
© 1999 Fairchild Semiconductor Corporation
USB1T11A • Rev. 1.0.2
2
www.fairchildsemi.com
Share Link: 