WED2DL32512V40BC データシートの表示（PDF） - White Electronic Designs Corporation
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WED2DL32512V40BC Datasheet PDF : 9 Pages
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WED2DL32512V
PIN DESCRIPTION
x36
CLK
4P
4N
2A, 2C, 2R, 2B
3A, 3B, 3C, 3T
4T, 5A, 5B, 5C,
5T, 6A, 6B, 6C, 6R
5L
5G
3G
3L
4M
4K
4E
7T
4F
4B
3R
(a) 6K, 6L, 6M, 6N,
7K, 7L, 7N, 7P
(b) 6E, 6F, 6G, 6H,
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
2K, 2L, 2M, 2N
2J, 4C, 4J, 4R, 5R,
6J
1A, 1F, 1J, 1M 1U
7A, 7F, 7J, 7M, 7U
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
2U
3U
4U
5U
Symbol
Input
SA0
SA1
SA
BWa
BWb
BWc
BWd
BWE
CLK
CE
ZZ
OE
ADSC
MODE
DQa
DQb
DQc
DQd
VDD
VDDQ
VSS
TMS
TDI
TDO
TCK
Type Description
Pulse The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of
CLK.
Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup
and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle.
Input
Input
Input
Input
Input
Input
Input
Input/
Output
BWa controls DQa’s and DQPa; BWb controls DQb’s and DQPb; BWc controls DQc’s and DQPc; BWd controls DQd’s and
DQPd.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP.
CE is sampled only when a new external address is loaded.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all
data in the memory array is retained. When active, all other inputs are ignored.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external
address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is also used to place
the chip into power-down state when CE is HIGH.
Mode: This input selects the burst sequence. A LOW on MODE selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is operating.
SRAM Data I/Os: Byte “a” is DQa’s; Byte “b” is DQb’s; Byte “c” is DQc’s;
Byte “d” is DQd’s. Input data must meet setup and hold times around rising edge of CLK.
Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating
Conditions for range.
Supply Ground: GND.
Input
Input
Output
Input
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
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