White Electronic Designs
WS512K32V-XXX
ADDRESS
DATA I/O
TIMING WAVEFORM - READ CYCLE
tRC
tAA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 1 (CS# = OE# = VIL, WE# = VIH)
ADDRESS
CS#
OE#
DATA I/O
tRC
tAA
tACS
tCLZ
tOE
tOLZ
HIGH IMPEDANCE
tCHZ
tOHZ
DATA VALID
READ CYCLE 2 (WE# = VIH)
WRITE CYCLE - WE# CONTROLLED
ADDRESS
CS#
WE#
DATA I/O
tWC
tAW
tCW
tAH
tAS
tWP
tWHZ
tOW
tDW
tDH
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
March 2006
Rev. 12
WRITE CYCLE - CS# CONTROLLED
ADDRESS
tAS
CS#
tWCWS32K32-XHX
tAW
tCW
tAH
WE#
DATA I/O
tWP
tDW
tDH
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
5
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