CYS25G0101DX-ATC(2007) データシートの表示（PDF） - Cypress Semiconductor
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CYS25G0101DX-ATC Datasheet PDF : 17 Pages
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Pin Configuration
The pin configuration for 120-pin Thin Quad Flatpack follows. [1, 2]
Figure 2. 120-Pin Thin Quad Flatpack Pin Configuration
Top View
CYS25G0101DX
LFI
RESET
D IA G L O O P
L IN E L O O P
LOOPA
VSSN
VCCN
VSSN
VSSN
SD
LOCKREF
RXD[0]
RXD[1]
RXD[2]
RXD[3]
VSSN
VDDQ
RXD[4]
RXD[5]
RXD[6]
RXD[7]
VSSN
VDDQ
RXCLK
VSSN
VDDQ
NC
NC
NC
NC
1
90
2
89
3
88
4
87
5
86
6
85
7
84
8
83
9
82
10
81
11
80
12
79
13
CYS25G0101DX
78
14
77
15
76
16
75
17
74
18
73
19
72
20
71
21
70
22
69
23
68
24
67
25
66
26
65
27
64
28
63
29
62
30
61
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
NC
VCCQ
VSSQ
REFCLK+
REFCLK–
NC
LOOPTIME
PW RDN
VSSN
VCCN
VSSN
TXCLKO
VSSN
VDDQ
TXD[0]
TXD[1]
TXD[2]
TXD[3]
VCCQ
VSSQ
VCCN
VSSN
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[9]
TXD[10]
TXD[11]
Notes
1. No connect (NC) pins are left unconnected or floating. Connecting any of these pins to the positive or negative power supply causes improper operation or failure of
the device.
2. Pins 113 and 119 are either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 are either no connect or VCCQ.
Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
Document Number: 38-02009 Rev. *K
Page 4 of 17
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