CYS25G0101DX-ATC(2007) データシートの表示（PDF） - Cypress Semiconductor
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CYS25G0101DX-ATC Datasheet PDF : 17 Pages
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CYS25G0101DX
CYS25G0101DX OC-48 SONET Transceiver (continued)
Pin Name I/O Characteristics
Signal Description
Loop Control Signals
DIAGLOOP LVTTL input
Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive
clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW,
received serial data is routed through the receive clock and data recovery. It is then
presented at the RXD[15:0] outputs.
LINELOOP LVTTL input
Line Loopback Control. When HIGH, received serial data is looped back from receive to
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.
LOOPA
LVTTL input
Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
LOOPTIME LVTTL input
Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock.
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.
Serial I/O
OUT±
Differential CML
output
Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable
of driving terminated 50Ω transmission lines or commercial fiber optic transmitter modules.
IN±
Differential CML
Differential Serial Data Input. This differential input accepts the serial data stream for
input
deserialization and clock extraction.
Power
VCCN
VSSN
VCCQ
VSSQ
VDDQ
Power
Ground
Power
Ground
Power
+3.3V supply (for digital and low speed IO functions)
Signal and power ground (for digital and low speed IO functions)
+3.3V quiet power (for analog functions)
Quiet ground (for analog functions)
+1.5V supply for HSTL outputs[4]
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed
to support reliable transfer of large quantities of data using high
speed serial links. It performs necessary clock and data
recovery, clock generation, serial-to-parallel conversion, and
parallel-to-serial conversion. CYS25G0101DX also provides
various loopback functions.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit wide
data paths.
Phase Align Buffer
Data from the input register is passed to a phase align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character clock.
Initialization of the phase align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is returned
HIGH, the present input clock phase, relative to TXCLKO, is set.
Once set, the input clock is allowed to skew in time up to half a
character period in either direction relative to REFCLK (that is,
±180°). This time shift allows the delay path of the character clock
(relative to REFLCK) to change due to operating voltage and
temperature not affecting the desired operation. FIFO_RST is an
asynchronous input. FIFO_ERR is the transmit FIFO Error
indicator. When HIGH, the transmit FIFO has either under or
overflowed. The FIFO is externally reset to clear the error
indication; or if no action is taken, the internal clearing
mechanism clears the FIFO in nine clock cycles. When the FIFO
is being reset, the output data is 1010.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52 MHz
external clock at the REFCLK input. It multiplies that clock by 16
to generate a bit rate clock for use by the transmit shifter. The
operating serial signaling rate and allowable range of REFCLK
frequencies is listed in Table 7 on page 11. The REFCLK phase
noise limits to meet SONET compliancy are shown in Figure 6
on page 13. The REFCLK± input is a standard LVPECL input.
Note
4. VDDQ equals VCC if interfacing to a parallel LVPECL interface.
Document Number: 38-02009 Rev. *K
Page 6 of 17
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