CYS25G0101DX-ATC(2007) データシートの表示（PDF） - Cypress Semiconductor
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CYS25G0101DX-ATC Datasheet PDF : 17 Pages
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CYS25G0101DX
Power Down Mode
CYS25G0101DX provides a global power down signal PWRDN.
When LOW, this signal powers down the entire device to a
minimal power dissipation state. RESET and FIFO_RST signals
should be asserted LOW along with PWRDN signal to ensure
low power dissipation.
DC Input Voltage ................................... –0.5V to VCC + 0.5V
Static Discharge Voltage........................................... > 1100V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Power Up Requirements
LVPECL Compliance
The CYS25G0101DX HSTL parallel I/O can be configured to
LVPECL compliance with slight termination modifications. On
the transmit side of the transceiver, the TXD[15:0] and TXCLKI
are made LVPECL compliant by setting VREF (reference voltage
of a LVPECL signal) to VCC – 1.33V. To emulate an LVPECL
signal on the receiver side, set the VDDQ to 3.3V and the trans-
mission lines needs to be terminated with the Thévenin equiv-
alent of Zο at LVPECL ref. The signal is then attenuated using a
series resistor at the driver end of the line to reduce the 3.3V
swing level to an LVPECL swing level (see Figure 10). This
circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO, and
RXCLK. The voltage divider is calculated assuming the system
is built with 50Ω transmission lines.
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
VCC Supply Voltage to Ground Potential ........–0.5V to +4.2V
VDDQ Supply Voltage to Ground Potential ......–0.5V to +4.2V
DC Voltage Applied to HSTL Outputs
in High Z State ..................................... –0.5V to VDDQ + 0.5V
DC Voltage Applied to Other Outputs
in High Z State ....................................... –0.5V to VCC + 0.5V
Output Current into LVTTL Outputs (LOW) ................. 30 mA
Table 1. DC Specifications—LVTTL
Power supply sequencing is not required if you are configuring
VDDQ=3.3V and all power supplies pins are connected to the
same 3.3V power supply.
Power supply sequencing is required if you are configuring
VDDQ=1.5V. Power is applied in the following sequence: VCC
(3.3) followed by VDDQ (1.5). Power supply ramping may occur
simultaneously as long as the VCC/VDDQ relationship is
maintained.
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDDQ
1.4V to 1.6V[4]
1.4V to 1.6V[4]
VCC
3.3V ± 10%
3.3V ± 10%
Parameter
Description
LVTTL Outputs
VOHT
Output HIGH Voltage
VOLT
Output LOW Voltage
IOS
Output Short Circuit Current
LVTTL Inputs
VIHT
VILT
IIHT
IILT
Capacitance
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
CIN
Input Capacitance
Test Conditions
VCC = Min, IOH = –10.0 mA
VCC = Min, IOL = 10.0 mA
VOUT = 0V
Low = 2.1V, High = VCC + 0.5V
Low = –3.0V, High = 0.8
VCC = Max, VIN = VCC
VCC = Max, VIN = 0V
VCC = Max, at f = 1 MHz
Min
Max
Unit
2.4
V
0.4
V
–20
–90
mA
2.1 VCC – 0.3
V
–0.3
0.8
V
50
µA
–50
µA
5
pF
Document Number: 38-02009 Rev. *K
Page 8 of 17
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