CYS25G0101DX-AEXC(2010) データシートの表示（PDF） - Cypress Semiconductor

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CYS25G0101DX-AEXC
(Rev.:2010)

SONET OC-48 Transceiver

Cypress Semiconductor 

CYS25G0101DX

Table 1. CYS25G0101DX OC-48 SONET Transceiver (continued)

Pin Name I/O Characteristics

Signal Description

Loop Control Signals

DIAGLOOP LVTTL input

Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive

clock and data recovery. It is then presented at the RXD[15:0] outputs. When LOW,

received serial data is routed through the receive clock and data recovery. It is then

presented at the RXD[15:0] outputs.

LINELOOP LVTTL input

Line Loopback Control. When HIGH, received serial data is looped back from receive to

transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data

passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA

are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.

LOOPA

LVTTL input

Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial

data is looped back from receive input buffer to transmit output buffer but is not routed

through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the

OUT± line driver is controlled by LINELOOP.

LOOPTIME LVTTL input

Loop Time Mode. When HIGH, the extracted receive bit clock replaces transmit bit clock.

When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.

Serial I/O

OUT±

Differential CML

output

Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable

of driving terminated 50 transmission lines or commercial fiber optic transmitter modules.

IN±

Differential CML

Differential Serial Data Input. This differential input accepts the serial data stream for

input

deserialization and clock extraction.

Power

VCCN

VSSN

VCCQ

VSSQ

VDDQ

Power

Ground

Power

Ground

Power

+3.3V supply (for digital and low speed IO functions)

Signal and power ground (for digital and low speed IO functions)

+3.3V quiet power (for analog functions)

Quiet ground (for analog functions)

+1.5V supply for HSTL outputs[4]

Note

4. VDDQ equals VCC if interfacing to a parallel LVPECL interface.

Document Number: 38-02009 Rev. *M

Page 6 of 18

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