AD9364 データシートの表示（PDF） - Analog Devices
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AD9364 Datasheet PDF : 32 Pages
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Data Sheet
Parameter1
Output Voltage
Minimum
Maximum
Output Current
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High
Low
Input Current
High
Low
Logic Outputs
Output Voltage
High
Low
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range
Symbol Min
Typ
0.5
VDD_GPO − 0.3
10
VDD_INTERFACE × 0.8
0
−10
−10
VDD_INTERFACE × 0.8
825
Input Differential Voltage
Threshold
−100
Receiver Differential Input
100
Impedance
Logic Outputs
Output Voltage
High
Low
1025
Output Differential Voltage
150
Output Offset Voltage
GENERAL-PURPOSE OUTPUTS
Output Voltage
High
Low
Output Current
SPI TIMING
SPI_CLK
Period
tCP
Pulse Width
tMP
SPI_ENB Setup to First SPI_CLK tSC
Rising Edge
Last SPI_CLK Falling Edge to tHC
SPI_ENB Hold
SPI_DI
Data Input Setup to
tS
SPI_CLK
Data Input Hold to SPI_CLK tH
SPI_CLK Rising Edge to Output
Data Delay
4-Wire Mode
tCO
3-Wire Mode
tCO
Bus Turnaround Time, Read
tHZM
VDD_GPO × 0.8
20
9
1
0
2
1
3
3
tH
1200
10
Bus Turnaround Time, Read
tHZS
0
Max
Unit
V
V
mA
VDD_INTERFACE
V
VDD_INTERFACE × 0.2 V
+10
μA
+10
μA
V
VDD_INTERFACE × 0.2 V
1575
mV
+100
mV
Ω
1375
mV
mV
mV
mV
V
VDD_GPO × 0.2
V
mA
ns
ns
ns
ns
ns
ns
8
ns
8
ns
tCO (max)
ns
tCO (max)
ns
AD9364
Test Conditions/Comments
Each differential input in the
pair
Programmable in 75 mV
steps
VDD_INTERFACE = 1.8 V
After baseband processor
(BBP) drives the last address
bit
After the AD9364 drives the
last data bit
Rev. C | Page 5 of 32
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