24AA040 データシートの表示（PDF） - Microchip Technology

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24AA040

4K SPI™ Bus Serial EEPROM

Microchip Technology 

25AA040/25LC040/25C040

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Name PDIP

CS

1

SO

2

WP

3

VSS

4

SI

5

SCK

6

HOLD 7

VCC

8

SOIC

1

2

3

4

5

6

7

8

TSSOP

Description

3

Chip Select Input

4

Serial Data Output

5

Write-Protect Pin

6

Ground

7

Serial Data Input

8

Serial Clock Input

1

Hold Input

2

Supply Voltage

2.1 Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go in Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes into the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

2.2 Serial Output (SO)

The SO pin is used to transfer data out of the 25XX040.

During a read cycle, data is shifted out on this pin after

the falling edge of the serial clock.

2.3 Write-Protect (WP)

This pin is a hardware write-protect input pin. When

WP is low, all writes to the array or STATUS register

are disabled, but any other operation functions

normally. When WP is high, all functions, including

nonvolatile writes operate normally. WP going low at

any time will reset the write enable latch and inhibit

programming, except when an internal write has

already begun. If an internal write cycle has already

begun, WP going low will have no effect on the write.

See Table 3-3 for Write-Protect Functionality Matrix.

2.4 Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

2.5 Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25XX040. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

2.6 Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25XX040 while in the middle of a serial sequence

without having to retransmit the entire sequence again

at a later time. It must be held high any time this func-

tion is not being used. Once the device is selected and

a serial sequence is underway, the HOLD pin may be

pulled low to pause further serial communication

without resetting the serial sequence. The HOLD pin

must be brought low while SCK is low, otherwise the

HOLD function will not be invoked until the next SCK

high-to-low transition. The 25XX040 must remain

selected during this sequence. The SI, SCK and SO

pins are in a high-impedance state during the time the

part is paused and transitions on these pins will be

ignored. To resume serial communication, HOLD must

be brought high while the SCK pin is low, otherwise

serial communication will not resume. Lowering the

HOLD line at any time will tri-state the SO line.

DS21204E-page 6

© 2006 Microchip Technology Inc.

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