A6595 データシートの表示（PDF） - Allegro MicroSystems
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A6595 Datasheet PDF : 10 Pages
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6595
8-BIT SERIAL-INPUT,
DMOS POWER DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
OUT N
OUTPUT
ENABLE
OUT N
C
50%
A
B
DATA
50%
tp
50%
D
E
50%
DATA
LOW = ALL OUTPUTS ENABLED
tp
HIGH = OUTPUT OFF
50%
DATA
LOW = OUTPUT ON
Dwg. WP-029-2
HIGH = ALL OUTPUTS DISABLED
50%
t PHL
t PLH
tf
90%
DATA
tr
10%
Dwg. WP-030-2
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 10 ns
C. Clock Pulse Width, tw(CLK) ............................................. 20 ns
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) .............................................. 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 µs
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Serial data present at the input is transferred to the shift
register on the rising edge of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information
towards the SERIAL DATA OUTPUT.
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With
the OUTPUT ENABLE input low, the outputs are controlled by
the state of their respective latches.
www.allegromicro.com
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