AD5433YRUZ-REEL7(2016) データシートの表示（PDF） - Analog Devices

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AD5433YRUZ-REEL7
(Rev.:2016)

8-/10-/12-Bit, High Bandwidth Multiplying DACs with Parallel Interface

Analog Devices 

AD5424/AD5433/AD5445

Parameter

Min

Output Capacitance

IOUT1

IOUT2

Digital Feedthrough

Analog THD

Digital THD

50 kHz fOUT

Output Noise Spectral Density2

SFDR Performance (Wide Band)

Clock = 10 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Clock = 25 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

SFDR Performance (Narrow Band)

Clock = 10 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Clock = 25 MHz

500 kHz fOUT

100 kHz fOUT

50 kHz fOUT

Intermodulation Distortion

Clock = 10 MHz

f1 = 400 kHz, f2 = 500 kHz

f1 = 40 kHz, f2 = 50 kHz

Clock = 25 MHz

f1 = 400 kHz, f2 = 500 kHz

f1 = 40 kHz, f2 = 50 kHz

POWER REQUIREMENTS

Power Supply Range

2.5

IDD

Power Supply Sensitivity

1 Guaranteed by design, not subject to production test.

2 Specification measured with OP27.

Typ Max

12 17

25 30

22 25

10 12

1

81

65

25

Unit

pF

pF

pF

pF

nV-s

dB

dB

nV√Hz

55

dB

63

dB

65

dB

50

dB

60

dB

62

dB

73

dB

80

dB

82

dB

70

dB

75

dB

80

dB

65

dB

72

dB

51

dB

65

dB

5.5

V

0.6

µA

0.4 5

µA

0.001

%/%

Data Sheet

Test Conditions/Comments

All 0s loaded

All 1s loaded

All 0s loaded

All 1s loaded

Feedthrough to DAC output with CS high and

alternate loading of all 0s and all 1s

VREF = 3.5 V p-p, all 1s loaded, f = 100 kHz

Clock = 10 MHz, VREF = 3.5 V

At 1 kHz

AD5445, VREF = 3.5 V

AD5445, VREF = 3.5 V

AD5445, VREF = 3.5 V

TA = 25°C, logic inputs = 0 V or VDD

Logic inputs = 0 V or VDD, T= −40°C to +125°C

ΔVDD = ±5%

Rev. E | Page 4 of 28

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