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Designing A Flyback Converter with Si9113 for Feeding the TE from U-Interface In ISDN

Vishay Semiconductors 

AN728

Vishay Siliconix

VIN

R3

STOP

R4

START

R5

8.8 V

–

+

ENABLE

START/STOP

Comparator

FIGURE 2. Start/Stop Programming

Current Sense

The Si9113 has two integrated comparators. The PWM

comparator, which is relatively slow, performs the current

mode control function by comparing the output of the error

amplifier with the current in the transformer primary. The

overcurrent limit comparator is a faster channel from the

current sense to the output driver and has a 100-ns typical

propagation time.

With the current sense resistor in the primary path, a voltage

signal which is proportional to the primary current is available

to control the switch-on period. This signal is used by the PWM

comparator as well as the overcurrent comparator. Selecting

the right value and type of resistor is very important, as it

determines the amount of power delivered to the load during

fault conditions. At the same time, a higher resistor value can

terminate the switching cycle prematurely and the circuit may

not be able to deliver enough power to the load. Normally, it is

recommended to derate the resistor by 20% of the value

required to deliver the full power.

Taking this in account the RSENSE value shall be estimated by

equation 3.

0.2

RSENSE v

VIN(min) DMAX

POUT

h

(3)

where, DMAX = Maximum Duty Ratio

POUT = Output Power (W)

h = Converter Efficiency

VIN(min) = Minimum Input Voltage (V)

Ideally, when the flyback converter is in discontinuous mode,

current rises at the rate determined by the input voltage and the

primary inductance of the transformer (Figure 3). In the real

world, however, a leading-edge spike is always created by the

MOSFET gate and output capacitance, the interlayer

capacitance of the primary and secondaries, the reverse

recovery of their respective rectifiers, and the inductive nature

of the current sense resistor. This leading edge spike may

cause the switch to turn off prematurely unless it is filtered out

by a low pass RC filter.

The leading edge spike includes a distinct component with a

period equal to the fall time of the MOSFET drain along with the

lower frequency oscillations. Obviously, it is difficult to estimate

the amplitude and burst-width of these spikes. One easy

approach is to measure on the oscilloscope, with a high

sampling rate, the total width and amplitude of the burst under

high-line and full-load conditions. Then design the RC network

to integrate all these spikes in the burst. Usually, for the 20-kHz

to 100-kHz converters, 200-ns to 50-ns time constants are a

good compromise.

Error Amplifier

Output

3.6 V

PWM Comparator

–

+

0.6 V

OC Comparator

–

+

(A)

(B)

(C)

FIGURE 3. Low Pass RC Filter at Current Sense

www.vishay.com S FaxBack 408-970-5600

2

Document Number: 71120

29-Feb-00

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