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Designing A Flyback Converter with Si9113 for Feeding the TE from U-Interface In ISDN

Vishay Semiconductors 

AN728

Vishay Siliconix

Compensation

Compensating the loop at one particular line and load is not

sufficient to ensure that the power supply will be equally stable

under other line and load conditions. The loop can be

compensated for all real-world conditions, but the margins will

not be consistent.

The Si9113 is designed with a high open loop gain (up to

60 dB) and 1.3-MHz unity gain bandwidth. A fast inner control

loop reduces propagation delays to achieve a good phase

margin at high crossover frequencies. This reduces the

compensation to the Type 2 network, where the low-frequency

zero is introduced at the power stage low-frequency pole and

the high-frequency pole is introduced at the output capacitor

ESR zero. This high-frequency pole makes the compensation

independent of the capacitor ESR and temperature, and also

prevents thin high-frequency noise spikes from being

amplified and transferred to the output.

Use the following guidelines to compensate the loop for the

Si9113 multi-output converter:

Calculate the effective output filter capacity Ceff and the

effective load resistor Reff of all the outputs at full load,

reflected to the main output through the turns ratio. Use these

values to locate the low-frequency power stage filter pole.

(Refer to Figure 6)

ǒ Ǔ CEFF

+

C11

)

NS2

NS1

C10 )

NS1 ) NS3

NS1

C4

(4)

+ 246.6 mF

For 800 mW of output power,

2

REFF

+

V3.3 V

POUT

(5)

+ 13.61 W

From equation 4 and 5, the power stage low-frequency pole is

calculated as:

FPP

+ 2p

1

REFF CEFF

(6)

+ 47 Hz

Calculate the power stage low-frequency gain. The

low-frequency power stage gain is equal to the change in the

power output per unit change in the error voltage, reflected by

the change in peak primary current. Or keeping the REFF the

same, the change in the output voltage per unit change in the

error amplifier output voltage. The energy transferred to the

output during the off cycle is equal to the amount of energy

stored in the transformer multiplied by the transformer and

secondary circuit efficiency. The power input to the converter

input is proportional to square of peak primary current (I-pk).

Document Number: 71120

29-Feb-00

PIN

+

1

2

LPǒIPKǓ2

fs

(7)

POUT

h

+

1

2

LPǒIPKǓ2

fs

or

Ǹ Ipk +

2 POUT

LP fs h

(8)

+ 192.45 mA

With the current sensing resistor R7= 2 W, a 1-mV change in

the error voltage will result in a 0.5-mA change in the peak

primary current. All other parameters remaining same, the

increase in the output power is:

PO

)

DPO

+

1

2

LPǒIPK ) DIPKǓ2

fs

h

(9)

+ 0.80416

For a fixed effective impedance REFF,

Ǹ VO ) DVO + ǒPO ) DPOǓ REFF

(10)

+ 3.3083 V

The

low

frequency

power

stage

gain

+

20

Log

DVO

1 mV

(11)

+ 18.4 dB

Plots of proposed close loop frequency response and power

stage frequency response (Figure 4) suggest the nature of the

error amplifier frequency response in terms of the location of

low-frequency zero at Fz and its gain at Fz.

50

40

30

20

10

0

–10

–20

–30

–40

–50

10

Closed Loop Gain

Error Amp Gain

Power Stage Gain

100

1,000

Frequency (Hz)

10,000 50,000

FIGURE 4. Calculated Loop Gain

The error amplifier low-frequency gain required from Figure 4

(DGain) = 23 dB.

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