AN728 データシートの表示（PDF） - Vishay Semiconductors
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AN728
Vishay Semiconductors
AN728 Datasheet PDF : 10 Pages
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AN728
Vishay Siliconix
R2 + R9
10
DGain
20
+ 282 k
Use 300 k
(15)
(12)
Phase
Margin
+
90
*
tan–1
FCO
Fp_esr
)
tan–1
FCO
Fz
*
tan–1
FCO
Fpp
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
10
Gain
Phase
100
1,000
Frequency (Hz)
10,000
180
150
120
90
60
30
0
–30
–60
–90
–120
–150
–180
50,000
FIGURE 5. Measured Loop Gain
Introduce the error amplifier low–frequency zero at 47 Hz.
C8 + 2p
1
fz
R2
+ 0.011 mF
(13)
Use 0.01 mF
Normally, capacitor manufacturers quote the capacitor ESR
values as maximums possible at a given frequency and
temperature. The actual ESR figure is unknown and also
varies with temperature. To make circuit stability independent
of ESR zero, add a high frequency pole below the worst-case
capacitor ESR zero location.
Fp_esr + 2p
1
R2
C3
+ 2p
1
300 k 100 pF
(14)
+ 5.3 kHz
Accounting for the phase lag, which results from the phase
inversion, the output filter, the error amplifier pole at the origin
and at the high frequency, and the phase lead resulting from
the error amplifier zero the phase margin can be estimated.
www.vishay.com S FaxBack 408-970-5600
4
The same procedure should be repeated for 30% of the output
power to make sure that the feedback loop is stable with
enough margin. Figure 5 shows the actual closed loop gain
and phase characteristics.
where, CEFF — Effective Output filter Capacity (F)
REFF — Effictive Output Load Resistance (R)
IPK — Peak Primary Current (A)
LP — Transformer Primary Inductance (H)
h — Converter Efficiency
fs — Switching Frequency (Hz)
FPP — Power Stage Low Frequency Pole (Hz)
fZ — Error Amp Low Frequency Zero (Hz)
fco — Close Loop Cross Over Frequency (Hz)
fp_esr — Capacitor ESR Zero (Hz)
Power Loss Consideration
In the restricted power mode of TE, every milliwatt of power
loss counts. Use the following guidelines to reduce the power
loses to a minimum, especially at high line:
D Switching Frequency: The switching losses incurred in
the transformer leakage inductance, the MOSFET gate,
MOSFET drain voltage and current cross over, the output
diode reverse recovery, and the control circuitry, are
proportional to the switching frequency. The lowest
possible operating frequency for a given form factor
should be used to keep the switching losses to a
minimum.
D Transformer: With an operating frequency range of
20 kHz, dc losses in the winding will usually be dominant.
Leakage inductor spikes from charging the MOSFET
output capacitor can also contribute to the losses, even
though these are very low at lower switching frequencies.
Select a core geometry and winding technique that
achieves a good coupling between the primary and
highest power output secondary. Refer to Vishay Siliconix
application note AN713 for flyback transformer design
guidelines.
D MOSFET switch: The dc and ac losses of the MOSFET
switch should be balanced. The low gate charge and low
gate-to-drain capacity MOSFET for a given rDS(on) should
be selected to keep the gate charge loss and drain
voltage and current cross over loss down. The Si3420DV,
a 200-V LITTLE FOOTR TSOP-6 device, is the best
choice for this application.
Document Number: 71120
29-Feb-00
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