CY7C1482V33-200BZI(2007) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1482V33-200BZI
(Rev.:2007)

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480V33

CY7C1482V33

CY7C1486V33

Pin Definitions

Pin Name

I/O

Description

A0, A1, A

Input-

Address Inputs Used to Select One of the Address Locations. Sampled at the

Synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are

sampled active. A1: A0 are fed to the two-bit counter.

BWA,BWB,BWC,BWD,

BWE,BWF,BWG,BWH

GW

BWE

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to

the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (ALL bytes are written, regardless of the values on

BWX and BWE).

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to

Clock

increment the burst counter when ADV is asserted LOW during a burst operation.

CE1

Input-

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1

is HIGH. CE1 is sampled only when a new external address is loaded.

CE2

Input-

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only

when a new external address is loaded.

CE3

Input-

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in

Synchronous conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only

when a new external address is loaded.

OE

Input-

Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO

Asynchronous pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are

tri-stated, and act as input data pins. OE is masked during the first clock of a read

cycle when emerging from a deselected state.

ADV

Input-

Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When

Synchronous asserted, it automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A1: A0 are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is

deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active

LOW. When asserted LOW, addresses presented to the device are captured in the

address registers. A1: A0 are also loaded into the burst counter. When ADSP and

ADSC are both asserted, only ADSP is recognized.

ZZ

Input-

ZZ “Sleep” Input, Active HIGH. When asserted HIGH places the device in a

Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs, DQPs

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained in

the memory location specified by the addresses presented during the previous clock

rise of the read cycle. The direction of the pins is controlled by OE. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed

in a tri-state condition.

VDD

Power Supply Power supply inputs to the core of the device.

VSS

VSSQ[2]

Ground

IO Ground

Ground for the core of the device.

Ground for the I/O circuitry.

VDDQ

IO Power Supply Power supply for the I/O circuitry.

Note

2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.

Document #: 38-05283 Rev. *H

Page 7 of 32

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