CY7C1486V33-250BGI(2007) データシートの表示（PDF） - Cypress Semiconductor

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CY7C1486V33-250BGI
(Rev.:2007)

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480V33

CY7C1482V33

CY7C1486V33

Pin Definitions (continued)

Pin Name

MODE

TDO

TDI

TMS

TCK

NC

I/O

Input Static

JTAG Serial

Output

Synchronous

JTAG Serial

Input

Synchronous

JTAG Serial

Input

Synchronous

JTAG Clock

-

Description

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to

VDD or left floating selects interleaved burst sequence. This is a strap pin and must

remain static during device operation. Mode Pin has an internal pull up.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If

the JTAG feature is not used, this pin must be disconnected. This pin is not available

on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be

connected to VSS. This pin is not available on TQFP packages.

No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are

address expansion pins and are not internally connected to the die.

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (tCO) is 3.0 ns

(250 MHz device).

The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports

secondary cache in systems using either a linear or inter-

leaved burst sequence. The interleaved burst order supports

Pentium and i486™ processors. The linear burst sequence is

suited for processors that use a linear burst sequence. The

burst order is user selectable, and is determined by sampling

the MODE input. Accesses can be initiated with either the

Processor Address Strobe (ADSP) or the Controller Address

Strobe (ADSC). Address advancement through the burst

sequence is controlled by the ADV input. A two-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the

rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE1, CE2, CE3 are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1

is HIGH. The address presented to the address inputs (A) is

stored into the address advancement logic and the Address

Register while being presented to the memory array. The

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 3.0 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always tri-stated during the first cycle of the access. After the

first cycle of the access, the outputs are controlled by the OE

signal. Consecutive single read cycles are supported. After the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output tri-states immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3 are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The write signals (GW, BWE, and BWX) and

ADV inputs are ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the write operation is controlled by BWE and BWX

signals.

The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides

byte write capability that is described in the “Truth Table for

Read/Write” on page 11. Asserting the Byte Write Enable input

(BWE) with the selected Byte Write (BWX) input, will selec-

tively write to only the desired bytes. Bytes not selected during

a Byte Write operation will remain unaltered. A synchronous

self-timed Write mechanism has been provided to simplify the

Write operations.

Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a

common I/O device, the Output Enable (OE) must be

deasserted HIGH before presenting data to the DQs inputs.

Doing so will tri-state the output drivers. As a safety

Document #: 38-05283 Rev. *H

Page 8 of 32

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