CY7C1482BV25(2011) データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C1482BV25
(Rev.:2011)

72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480BV25

CY7C1482BV25, CY7C1486BV25

Pin Definitions (continued)

Pin Name

MODE

TDO

TDI

TMS

TCK

NC

I/O

Description

Input Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence. This is a strap pin and must remain static

during device operation. Mode pin has an internal pull up.

JTAG Serial

Output

Synchronous

Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG

feature is not used, this pin must be disconnected. This pin is not available on TQFP packages.

JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous is not used, this pin can be disconnected or connected to VDD. This pin is not available on

TQFP packages.

JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous is not used, this pin can be disconnected or connected to VDD. This pin is not available on

TQFP packages.

JTAG Clock

-

Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected

to VSS. This pin is not available on TQFP packages.

No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address

expansion pins and are not internally connected to the die.

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).

The

CY7C1480BV25/CY7C1482BV25/CY7C1486BV25

supports secondary cache in systems using either a linear or

interleaved burst sequence. The interleaved burst order

supports Pentium and i486 processors. The linear burst

sequence is suited for processors that use a linear burst

sequence. The burst order is user selectable, and is determined

by sampling the MODE input. Accesses can be initiated with

either the Processor Address Strobe (ADSP) or the Controller

Address Strobe (ADSC). Address advancement through the

burst sequence is controlled by the ADV input. A two-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the rest

of the burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW) overrides all byte write inputs and writes data to all

four bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide easy bank selection

and output tristate control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE1, CE2, CE3 are all asserted active, and (3) the write

signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

Register while being presented to the memory array. The

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data is

allowed to propagate through the output register and onto the

data bus within 3.0 ns (250-MHz device) if OE is active LOW. The

only exception occurs when the SRAM is emerging from a

deselected state to a selected state; its outputs are always

tristated during the first cycle of the access. After the first cycle

of the access, the outputs are controlled by the OE signal.

Consecutive single read cycles are supported. After the SRAM

is deselected at clock rise by the chip select and either ADSP or

ADSC signals, its output tristates immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are

satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,

CE2, CE3 are all asserted active. The address presented to A is

loaded into the address register and the address advancement

logic while being delivered to the memory array. The write signals

(GW, BWE, and BWX) and ADV inputs are ignored during this

first cycle.

ADSP-triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW is

HIGH, then the BWE and BWX signals control the write

operation.

The

CY7C1480BV25/CY7C1482BV25/CY7C1486BV25

provides Byte Write capability that is described in the Truth Table

for Read/Write on page 12. Asserting the Byte Write Enable input

(BWE) with the selected Byte Write (BWX) input, selectively

writes to only the desired bytes. Bytes not selected during a byte

write operation remain unaltered. A synchronous self-timed write

mechanism is provided to simplify the write operations.

Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is

a common I/O device, the Output Enable (OE) must be

deasserted HIGH before presenting data to the DQs inputs.

Doing so tristates the output drivers. As a safety precaution, DQs

are automatically tristated whenever a write cycle is detected,

regardless of the state of OE.

Document Number: 001-15143 Rev. *H

Page 9 of 34

[+] Feedback

Share Link: