D8255 データシートの表示（PDF） - Digital Core Design

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D8255

PROGRAMMABLE INTERVAL TIMER

Digital Core Design 

Group A and Group B Controls - The func-

tional configuration of each port is pro-

grammed by the systems software. In es-

sence, the CPU “outputs”' a control word to

the D8255. The control word contains infor-

mation such as “mode”', “bit set”, “bit reset”,

etc., that initializes the functional configura-

tion of the D8255. Each of the Control blocks

(Group A and Group B) accepts “commands”

from the Read/Write Control Logic, receives

“control words” from the internal data bus and

issues the proper commands to its associated

ports.

Group A - Port A and upper half of Port C

Group B - Port B and lower half of Port C

The control word register can be both written

and read. Figure below shows the control

word format for both Read and Write opera-

tions. When the control word is read, bit D7

will always be a logic “1”, as this implies con-

trol word mode information.

clk

rst

Group A

Control

Group A

Port A

portai[7:0]

portao[7:0]

datai

datao

a1

a0

rd

wr

cs

Data Bus

Buffer

&

Control

Logic

Group A

Port C

Upper

Group B

Port C

Lower

portci[7:4]

portco[7:4]

portci[3:0]

portco[3:0]

Group B

Control

Group B

Port B

portbi[7:0]

portbo[7:0]

Ports A, B, and C - The D8255 contains

three 8-bit ports. All can be configured in a

wide variety of functional characteristics by

the system software but each has its own

special features or “personality” to further

enhance the power and flexibility of the

D8255.

Port A - One 8-bit data output latch/buffer

and one 8-bit input latch buffer. Both „pull-up''

and “pulldown” bus hold devices are present

on Port A.

Port B - One 8-bit data input/output

latch/buffer. Only „pull-up'' bus hold devices

are present on Port B.

Port C - One 8-bit data output latch/buffer

and one 8-bit data input buffer (no latch for

input). This port can be divided into two 4-bit

ports under the mode control. Each 4-bit port

contains a 4-bit latch and it can be used for

the control signal outputs and status signal

inputs in conjunction with ports A and B. Only

„pull-up'' bus hold devices are present on Port

C.

DELIVERABLES

♦ Source code:

◊ VHDL Source Code or/and

◊ VERILOG Source Code or/and

◊ ALTERA’s Megafunction or/and

◊ EDIF netlist

♦ VHDL & VERILOG test bench environ-

ment

◊ Active-HDL automatic simulation mac-

ros

◊ ModelSim automatic simulation macros

◊ Tests with reference responses

♦ Technical documentation

◊ Installation notes

◊ HDL core specification

◊ Datasheet

♦ Synthesis scripts

♦ Example application

♦ Technical support

◊ IP Core implementation support

◊ 3 months maintenance

● Delivery the IP Core updates, mi-

nor and major versions changes

● Delivery the documentation up-

dates

● Phone & email support

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are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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