HCPL0600 データシートの表示（PDF） - Fairchild Semiconductor

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HCPL0600

High Speed-10 MBit/s Logic Gate Optocouplers

Fairchild Semiconductor 

Pulse Gen.

tf = tr = 5 ns

ZO = 50 Ω

1

2

Input

Monitor

3

(IF)

47Ω 4

VCC 8

7

.1µf

Bypass

6

GND 5

+5V

Pulse Gen.

ZO = 50 Ω

tf = tr = 5 ns

IF

Input

RL

Monitoring

Node

Output

(VO)

CL

RM

Test Circuit for HCPL0600,

HCPL0601 and HCPL0611

Dual Channel

1

VCC 8

2

7

3

6

4

5

GND

+5 V

RL

0.1µF

Bypass

Output VO

Monitoring

Node

CL*

Input

(I F)

tPHL

Output

(VO)

Output

(VO)

tf

Test Circuit for HCPL0630,

HCPL0631 and HCPL0661

I F = 7.5 mA

I F = 3.75 mA

tPLH

90%

10 %

1.5 V

tr

Fig. 21 Test Circuit and Waveforms for tPLH, tPHL, tr and tf.

Pulse

Generator

tr = 5ns

ZO = 50Ω

1

7.5 mA

2

3

4

Input

Monitor

(V E)

+5V

VCC

8

7

.1µf

bypass

6

5

GND

RL

Output

(VO)

CL

Input

(VE )

tEHL

Output

(VO)

Fig. 22 Test Circuit tEHL and tELH.

t ELH

3.0 V

1.5 V

1.5 V

11

HCPL0600, HCPL0601, HCPL0611, HCPL0630, HCPL0631, HCPL0661 Rev. 1.0.1

www.fairchildsemi.com

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