HM62256A データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HM62256A

32,768-word ×8-bit High Speed CMOS Static RAM

Hitachi -> Renesas Electronics 

HM62256A Series

Low VCC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L/L-SL version.

HM62256A Series

Parameter

Symbol Min Typ*1 Max Unit Test conditions

———————————————————————————————————————————————–

VCC for data retention

VDR

2

—

—

V

CS ≥ VCC – 0.2 V, Vin ≥ 0 V

———————————————————————————————————————————————–

Data retention current

ICCDR —

0.2

30*2 µA VCC = 3.0 V, Vin ≥ 0 V

——————————————–

—

0.2

10*3 µA CS ≥ VCC – 0.2 V

———————————————————————————————————————————————–

Chip deselect to data retention time tCDR 0

—

—

ns See retention waveform

——————————————————————————————————––

Operation recovery time

tR

tRC*4 —

—

ns

———————————————————————————————————————————————–

Low VCC Data Retention Timing Waveform

VCC

4.5 V

2.2 V

VDR

CS

0V

t CDR

Data retention mode

tR

CS ≥ VCC – 0.2 V

Notes: 1 Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.

2. 20 µA max at Ta = 0 to +40°C. (only for L-version)

3. 3 µA max at Ta = 0 to +40°C. (only for L-SL version)

4. tRC = read cycle time.

5. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data

retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state.

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