HV6506 データシートの表示（PDF） - Supertex Inc

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HV6506

32-Channel LCD Driver with Separate Backplane Output

Supertex Inc 

Functional Block Diagram

VPP

Polarity

Latch Enable

VDD

Data Input

Clock

DIR

32-Bit

Shift

Register

Latch

Latch

Data Out

Latch

Latch

GND

HV6506

HVOUT1

HVOUT2

(Outputs 3 to 30

not shown)

HVOUT31

HVOUT32

BPOUT

Function Table

Inputs

Function

Data CLK

LE

POL

Load S/R

H or L

↑

L

H

Load latches

X

H or L

L

H

X

H or L

L

L

All high

H

↑

H

L

L

↑

H

H

All low

H

↑

H

H

L

↑

H

L

L

↑

H

H

Transparent

H

↑

H

H

Mode

L

↑

H

L

H

↑

H

L

R/L Shift

X

↑

X

X

X

↑

X

X

Notes:

H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition.

* = dependent on previous stage’s state before the last CLK or last LE high.

Outputs

DIR

Shift Reg

HV Outputs Data Out

1 2…32 1

2…32

X

H or L *…*

*

*…*

*

X

*

*…*

*

*…*

*

X

*

*…*

*

*…*

*

X

H

*…*

H

*…*

*

X

L

*…*

H

*…*

*

X

H

*…*

L

*…*

*

X

L

*…*

L

*…*

*

X

L

*…*

H

*…*

*

X

H

*…*

L

*…*

*

X

L

*…*

L

*…*

*

X

H

*…*

H

*…*

*

H

Qn → Qn+1

*

*…*

Q32

L

Qn → Qn-1

*

*…*

Q1

12

BP

OUT

*

H

H

L

L

H

H

L

H

H

L

L

12-135

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