HY27SS(08/16)561M データシートの表示（PDF） - Hynix Semiconductor

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HY27SS(08/16)561M

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory

Hynix Semiconductor 

HY27SS(08/16)561M Series

HY27US(08/16)561M Series

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash

Data Input

Data Input bus operations are used to input the data to be programmed.

Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command Latch Enable is Low and Read

Enable is High. The data is latched on the rising edge of the Write Enable signal. The data is input sequentially using

the Write Enable signal.

See Figure 23 and Tables 14 and 15 for details of the timings requirements.

Data Output

Data Output bus operations are used to read: the data in the memory array, the Status Register, the Electronic Signa-

ture and the Serial Number. Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is

Low, and Command Latch Enable is Low. The data is output sequentially using the Read Enable signal.

See Figure 24 and Table 15 for details of the timings requirements.

Write Protect

Write Protect bus operations are used to protect the memory against program or erase operations. When the Write

Protect signal is Low the device will not accept program or erase operations and so the contents of the memory array

cannot be altered. The Write Protect signal is not latched by Write Enable to ensure protection even during power-up.

Standby

When Chip Enable is High the memory enters Standby mode, the device is deselected, outputs are disabled and power

consumption is reduced.

Rev 0.7 / Oct. 2004

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