HY27SS(08/16)561M データシートの表示（PDF） - Hynix Semiconductor

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HY27SS(08/16)561M

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory

Hynix Semiconductor 

HY27SS(08/16)561M Series

HY27US(08/16)561M Series

256Mbit (32Mx8bit / 16Mx16bit) NAND Flash

Vcc

GND

I/O8-I/O15, x16

CE

I/O0-I/O7, x8/x16

RE

NAND

WE

Flash

RB

ALE

CLE

WP

Vss

Figure 1: Logic Diagram

I/O8-15

I/O0-7

ALE

CLE

CE

RE

RB

WE

WP

VCC

VSS

GND

NC

Data Input/Outputs for x16 Device

Data Input/Output, Address Inputs, or Com-

mand Inputs for x8 and x16 device

Address Latch Enable

Command Latch Enable

Chip Enable

Read Enable

Read/Busy (open-drain output)

Write Enable

Write Protect

Supply Voltage

Ground

GND Input for Spare Area Enable

Not Connected Internally

Table 1: Signal Name

Address

Register/Counter

ALE

CLE

WE

CE

WP

RE

Command

Interface

Logic

Command Register

P/E/R

Controller,

High Voltage

Generator

NAND Flash

Memory Array

Page Buffer

Cache Register

Y Decoder

Rev 0.7 / Oct. 2004

I/O Buffers &

Latches

RB

I/O0-I/O7, x8/x16

I/O8-I/O15, x16

Figure 2. LOGIC BLOCK DIAGRAM

4

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