INTEL82801 データシートの表示（PDF） - Intel

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INTEL82801

Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub

Intel 

Signal Description

2.3

PCI Interface

Table 2-3. PCI Interface Signals (Sheet 1 of 3)

Name Type

Description

AD[31:0]

PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first

I/O

clock of a transaction, AD[31:0] contain a physical address (32 bits). During

subsequent clocks, AD[31:0] contain data. The ICH drives all 0’s on AD[31:0] during the

address phase of PCI Interrupt Acknowledge cycles.

Bus Command and Byte Enables: The command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction,

C/BE[3:0]# define the bus command. During the data phase, C/BE[3:0]# define the

Byte Enables.

C/BE[3:0]#

0000

0001

0010

0011

C/BE[3:0]# I/O

0110

0111

1010

1011

1100

1110

1111

Command Type

Interrupt Acknowledge

Special Cycle

I/O Read

I/O Write

Memory Read

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple

Memory Read Line

Memory Write and Invalidate

DEVSEL#

FRAME#

IRDY#

TRDY#

NOTE: All command encodings not shown are reserved. The ICH does not decode

reserved values, and, therefore, does not respond if a PCI master generates a

cycle using one of the reserved values.

Device Select: The ICH asserts DEVSEL# to claim a PCI transaction. As an output,

the ICH asserts DEVSEL# when a PCI master peripheral attempts an access to an

I/O

internal ICH register or man memory. As an input, DEVSEL# indicates the response to

an ICH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading

edge of PCIRST#. DEVSEL# remains tri-stated by the ICH until driven by a Target

device.

Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and

duration of a PCI transaction. While the initiator asserts FRAME#, data transfers

I/O

continue. When the initiator negates FRAME#, the transaction is in the final data

phase. FRAME# is an input to the ICH when the ICH is the target, and FRAME# is an

output from the ICH when the ICH is the Initiator. FRAME# remains tri-stated by the

ICH until driven by an Initiator.

Initiator Ready: IRDY# indicates the ICH's ability, as an Initiator, to complete the

current data phase of the transaction. It is used in conjunction with TRDY#. A data

phase is completed on any clock both IRDY# and TRDY# are sampled asserted.

I/O During a write, IRDY# indicates the ICH has valid data present on AD[31:0]. During a

read, it indicates the ICH is prepared to latch data. IRDY# is an input to the ICH when

the ICH is the Target and an output from the ICH when the ICH is an Initiator. IRDY#

remains tri-stated by the ICH until driven by an Initiator.

Target Ready: TRDY# indicates the ICH's ability as a Target to complete the current

data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase

is completed when both TRDY# and IRDY# are sampled asserted. During a read,

I/O

TRDY# indicates that the ICH, as a Target, has placed valid data on AD[31:0]. During a

write, TRDY# indicates the ICH, as a Target is prepared to latch data. TRDY# is an

input to the ICH when the ICH is the Initiator and an output from the ICH when the ICH

is a Target. TRDY# is tri-stated from the leading edge of PCIRST#. TRDY# remains tri-

stated by the ICH until driven by a target.

2-2

82801AA and 82801AB Datasheet

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