INTEL82801 データシートの表示（PDF） - Intel

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INTEL82801

Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub

Intel 

5.2 LPC Bridge (with System & Management Functions) (D31:F0)....................5-4

5.2.1 LPC Interface ...................................................................................5-4

5.2.1.1 LPC Cycle Types..............................................................5-5

5.2.1.2 Start Field Definition .........................................................5-5

5.2.1.3 Cycle Type / Direction (CYCTYPE + DIR)........................5-6

5.2.1.4 SIZE..................................................................................5-6

5.2.1.5 SYNC................................................................................5-6

5.2.1.6 SYNC Time-out ................................................................5-7

5.2.1.7 SYNC Error Indication ......................................................5-7

5.2.1.8 LFRAME# Usage..............................................................5-7

5.2.1.9 I/O Cycles .........................................................................5-9

5.2.1.10 Bus Master Cycles............................................................5-9

5.2.1.11 Configuration and ICH Implications ..................................5-9

5.3 DMA Operation (D31:F0) ..............................................................................5-9

5.3.1 Channel Priority .............................................................................5-10

5.3.2 Address Compatibility Mode ..........................................................5-11

5.3.3 Summary of DMA Transfer Sizes ..................................................5-11

5.3.4 Autoinitialize...................................................................................5-12

5.3.5 Software Commands .....................................................................5-12

5.4 PCI DMA .....................................................................................................5-13

5.4.1 PCI DMA Expansion Protocol ........................................................5-13

5.4.2 PCI DMA Expansion Cycles ..........................................................5-14

5.4.3 DMA Addresses .............................................................................5-15

5.4.4 DMA Data Generation....................................................................5-15

5.4.5 DMA Byte Enable Generation........................................................5-15

5.4.6 DMA Cycle Termination .................................................................5-16

5.5 LPC DMA ....................................................................................................5-16

5.5.1 Asserting DMA Requests...............................................................5-16

5.5.2 Abandoning DMA Requests...........................................................5-17

5.5.3 General Flow of DMA Transfers ....................................................5-17

5.5.4 Terminal Count ..............................................................................5-18

5.5.5 Verify Mode....................................................................................5-18

5.5.6 DMA Request Deassertion ............................................................5-18

5.5.7 SYNC Field / LDRQ# Rules ...........................................................5-19

5.6 8254 Timers (D31:F0).................................................................................5-20

5.6.1 Timer Programming .......................................................................5-20

5.6.2 Reading from the Interval Timer ....................................................5-21

5.7 8259 Interrupt Controllers (PIC) (D31:F0)...................................................5-23

5.7.1 Interrupt Handling ..........................................................................5-23

5.7.2 Initialization Command Words (ICWx) ...........................................5-25

5.7.3 Operation Command Words (OCW) ..............................................5-26

5.7.4 Modes of Operation .......................................................................5-26

5.7.5 Masking Interrupts .........................................................................5-29

5.7.6 Steering PCI Interrupts ..................................................................5-29

5.8 Advanced Interrupt Controller (APIC) (D31:F0) ..........................................5-30

5.8.1 Interrupt Handling ..........................................................................5-30

5.8.2 Interrupt Mapping...........................................................................5-30

5.8.3 APIC Bus Functional Description...................................................5-31

5.8.3.1 Physical Characteristics of APIC ....................................5-31

5.8.3.2 APIC Bus Arbitration.......................................................5-31

5.8.3.3 Bus Message Formats....................................................5-32

82801AA and 82801AB Datasheet

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