INTEL82801 データシートの表示（PDF） - Intel
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INTEL82801 Datasheet PDF : 414 Pages
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5.9 Serial Interrupt (D31:F0) .............................................................................5-37
5.9.1 Start Frame....................................................................................5-37
5.9.2 Data Frames ..................................................................................5-37
5.9.3 Stop Frame ....................................................................................5-38
5.9.4 Specific Interrupts not Supported via SERIRQ ..............................5-38
5.9.5 Data Frame Format .......................................................................5-39
5.10 Real Time Clock (D31:F0) ..........................................................................5-40
5.10.1 Update Cycles ...............................................................................5-40
5.10.2 Interrupts........................................................................................5-41
5.10.3 Lockable RAM Ranges ..................................................................5-41
5.10.4 Century Rollover ............................................................................5-41
5.10.5 Clearing Battery-Backed RTC RAM...............................................5-41
5.11 Processor Interface (D31:F0) .....................................................................5-43
5.11.1 Processor Interface Signals ...........................................................5-43
5.11.2 Dual Processor Issues (ICH: 82801AA only) .................................5-45
5.11.2.1 Signal Differences (ICH: 82801AA only) ........................5-45
5.11.2.2 Power Management (ICH: 82801AA only) .....................5-45
5.11.3 Speed Strapping for Processor......................................................5-46
5.12 Power Management (D31:F0) ....................................................................5-47
5.12.1 ICH and System Power States ......................................................5-47
5.12.2 System Power Planes....................................................................5-48
5.12.3 SMI#/SCI Generation.....................................................................5-49
5.12.4 Dynamic System Clock Control .....................................................5-50
5.12.4.1 Entering/Exiting the C1 State .........................................5-50
5.12.4.2 Entering/Exiting the C2 State .........................................5-51
5.12.4.3 Throttling Using STPCLK# .............................................5-51
5.12.4.4 Transition Rules Among S0/Cx and Throttling States ....5-52
5.12.5 Sleep States ..................................................................................5-52
5.12.5.1 Sleep State Overview.....................................................5-52
5.12.5.2 Initiating Sleep State ......................................................5-52
5.12.5.3 Exiting Sleep States .......................................................5-53
5.12.5.4 Sx-G3-Sx, Handling Power Failures...............................5-54
5.12.6 Thermal Management....................................................................5-55
5.12.6.1 THRM# Signal ................................................................5-55
5.12.6.2 THRM# Initiated Passive Cooling...................................5-55
5.12.6.3 Processor Initiated Passive Cooling
(Via Programmed Duty Cycle on STPCLK#)..................5-56
5.12.6.4 Active Cooling ................................................................5-56
5.12.7 Event Input Signals and Their Usage ............................................5-56
5.12.7.1 PWRBTN#—Power Button.............................................5-56
5.12.7.2 RI#—Ring Indicate .........................................................5-57
5.12.7.3 PME#—PCI Power Management Event.........................5-57
5.12.8 Alt Access Mode ............................................................................5-57
5.12.8.1 Write Only Registers with Read Paths in
Alternate Access Mode5-58
5.12.8.2 PIC Reserved Bits ..........................................................5-59
5.12.8.3 Read Only Registers with Write Paths in
Alternate Access Mode ..................................................5-60
5.12.9 System Power Supplies, Planes, and Signals ...............................5-60
5.12.10 Clock Generators ...........................................................................5-61
5.12.11 Legacy Power Management Theory of Operation .........................5-61
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82801AA and 82801AB Datasheet
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