INTEL82801 データシートの表示（PDF） - Intel

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INTEL82801

Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) I/O Controller Hub

Intel 

5.13 System Management (D31:F0)...................................................................5-62

5.13.1 Overview of System Management Functions ................................5-62

5.13.2 Theory of Operation .......................................................................5-62

5.13.2.1 Handling an ECC Error or Other Memory Error..............5-63

5.13.3 Alert on LAN* (ICH: 82801AA only) ...............................................5-63

5.14 IDE Controller (D31:F1) ..............................................................................5-66

5.14.1 PIO Transfers.................................................................................5-67

5.14.1.1 PIO IDE Timing Modes...................................................5-67

5.14.1.2 IORDY Masking..............................................................5-68

5.14.1.3 PIO 32 Bit IDE Data Port Accesses................................5-68

5.14.1.4 PIO IDE Data Port Prefetching and Posting ...................5-68

5.14.2 Bus Master Function ......................................................................5-68

5.14.2.1 Physical Region Descriptor Format ................................5-68

5.14.2.2 Line Buffer ......................................................................5-69

5.14.2.3 Bus Master IDE Timings.................................................5-69

5.14.2.4 Interrupts ........................................................................5-70

5.14.2.5 Bus Master IDE Operation..............................................5-70

5.14.2.6 Error Conditions..............................................................5-71

5.14.2.7 8237 Like Protocol..........................................................5-71

5.14.3 Ultra ATA/33 Protocol ....................................................................5-72

5.14.3.1 Signal Descriptions.........................................................5-72

5.14.3.2 Operation........................................................................5-73

5.14.3.3 CRC Calculation .............................................................5-73

5.14.3.4 Synchronous DMA Timings ............................................5-73

5.14.3.5 Ultra ATA/66 (ICH: 82801AA only) .................................5-74

5.15 USB Controller (Device 31:Function 2).......................................................5-74

5.15.1 Data Structures in Main memory ...................................................5-75

5.15.1.1 Frame List Pointer ..........................................................5-75

5.15.1.2 Transfer Descriptor (TD).................................................5-76

5.15.1.3 Queue Head (QH) ..........................................................5-80

5.15.2 Data Transfers To/From Main Memory..........................................5-81

5.15.2.1 Executing the Schedule..................................................5-81

5.15.2.2 Processing Transfer Descriptors ....................................5-81

5.15.2.3 Command Register, Status Register, and

TD Status Bit Interaction.................................................5-82

5.15.2.4 Transfer Queuing............................................................5-83

5.15.3 Data Encoding and Bit Stuffing ......................................................5-86

5.15.4 Bus Protocol...................................................................................5-86

5.15.4.1 Bit Ordering ....................................................................5-86

5.15.4.2 SYNC Field.....................................................................5-86

5.15.4.3 Packet Field Formats......................................................5-87

5.15.4.4 Address Fields................................................................5-88

5.15.4.5 Frame Number Field.......................................................5-88

5.15.4.6 Data Field .......................................................................5-88

5.15.4.7 Cyclic Redundancy Check (CRC) ..................................5-88

5.15.5 Packet Formats..............................................................................5-89

5.15.5.1 Token Packets................................................................5-89

5.15.5.2 Start of Frame Packets...................................................5-89

5.15.5.3 Data Packets ..................................................................5-90

5.15.5.4 Handshake Packets........................................................5-90

5.15.5.5 Handshake Responses ..................................................5-90

82801AA and 82801AB Datasheet

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