KSZ8863MLL データシートの表示（PDF） - Micrel

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KSZ8863MLL

Integrated 3-Port 10/100 Managed Switch with PHYs

Micrel 

Micrel, Inc.

KSZ8863MLL/FLL//RLL

List of Figures

Figure 1. Typical Straight Cable Connection ....................................................................................................................... 19

Figure 2. Typical Crossover Cable Connection ................................................................................................................... 20

Figure 3. Auto-Negotiation and Parallel Operation .............................................................................................................. 21

Figure 4. Destination Address Lookup Flow Chart, Stage 1 ................................................................................................ 25

Figure 5. Destination Address Resolution Flow Chart, Stage 2........................................................................................... 26

Figure 6. 802.1p Priority Field Format ................................................................................................................................. 35

Figure 7. Tail Tag Frame Format ......................................................................................................................................... 37

Figure 8. Tail Tag Rules ....................................................................................................................................................... 38

Figure 9. EEPROM Configuration Timing Diagram ............................................................................................................. 40

Figure 10. SPI Write Data Cycle .......................................................................................................................................... 42

Figure 11. SPI Read Data Cycle .......................................................................................................................................... 42

Figure 12. SPI Multiple Write ............................................................................................................................................... 42

Figure 13. SPI Multiple Read ............................................................................................................................................... 43

Figure 14. Far-End Loopback Path ...................................................................................................................................... 43

Figure 15. Near-End (Remote) Loopback Path ................................................................................................................... 44

Figure 16. EEPROM Interface Input Timing Diagram.......................................................................................................... 94

Figure 17. EEPROM Interface Output Timing Diagram ....................................................................................................... 94

Figure 18. MAC Mode MII Timing – Data Received from MII .............................................................................................. 95

Figure 19. MAC Mode MII Timing – Data Transmitted to MII ............................................................................................. 95

Figure 20. PHY Mode MII Timing – Data Received from MII............................................................................................... 96

Figure 21. PHY Mode MII Timing – Data Transmitted to MII ............................................................................................... 96

Figure 22. RMII Timing – Data Received from RMII ............................................................................................................ 97

Figure 23. RMII Timing – Data Transmitted to RMII ............................................................................................................ 97

Figure 24. I2C Input Timing .................................................................................................................................................. 98

Figure 25. I2C Start Bit Timing ............................................................................................................................................. 98

Figure 28. SPI Input Timing ............................................................................................................................................... 100

Figure 29. SPI Output Timing............................................................................................................................................. 101

Figure 30. Auto-Negotiation Timing ................................................................................................................................... 102

Figure 31. MDC/MDIO Timing............................................................................................................................................ 103

Figure 32. Reset Timing..................................................................................................................................................... 104

Figure 33. Recommended Reset Circuit ............................................................................................................................ 105

Figure 34. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output.................................................... 105

January 27, 2014

10

Revision 1.5

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