LV8483CS データシートの表示（PDF） - SANYO -> Panasonic
部品番号
コンポーネント説明
メーカー
LV8483CS Datasheet PDF : 9 Pages
| |||
LV8483CS
I2C bus transmission method
Start and stop conditions
The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
data transfer operation.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Start condition
Stop condition
SCL
SDA
th1
th3
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data.
Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end.
Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released,
and SDA is set to low at the receiving end, causing the ACK signal to be sent.
When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the
receiving end releases SDA at the falling edge of the ninth SCL clock.
Start
M
L
AM
S Slave address S W C S
B
B
KB
Data
L AM
SCS
BKB
Data
LA
SC
BK
Stop
SCL
SDA
1st byte
S7 S6 S5 S4 S3 S2 S1 0
2nd byte
A7 A6 A5 A4 A3 A2 A1 A0
3rd byte
D7 D6 D5 D4 D3 D2 D1 D0
Number of Slave Address is 0110011. (S7→S1)
No.A1609-6/9
Share Link: 