M69AW024BL60ZB8T データシートの表示（PDF） - STMicroelectronics

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M69AW024BL60ZB8T

16 Mbit (1M x16) 3V Asynchronous PSRAM

STMicroelectronics 

M69AW024B

Table 2. Operating Modes

Operation

E2 E1 W

G

LB UB A0-A19 DQ0-DQ7

DQ8-

DQ15

ICC

Data Re-

tention

Standby (Deselect) VIH VIH X (1) X (1) X (1) X (1) X (1)

Hi-Z

Hi-Z

ISB

Yes

Output Disabled (2) VIH VIL VIH VIH X (1) X (1) Note (4)

Hi-Z

Hi-Z

ICC

Yes

Output Disabled

(No Read)

VIH VIL VIH VIL VIH VIH Valid

Hi-Z

Hi-Z

ICC

Yes

Word Read(5)

VIH VIL VIH VIL

VIL(6)

Valid

Output Valid

ICC

Yes

Word Read

VIH VIL VIH VIL VIL VIL Valid

Output Valid

ICC

Yes

Upper Byte Write VIH VIL VIL VIH VIH VIL Valid

Invalid Input Valid ICC

Yes

Lower Byte Write VIH VIL VIL VIH VIL VIH Valid Input Valid Invalid

ICC

Yes

Word Write

VIH VIL VIL VIH VIL VIL Valid Input Valid Input Valid ICC

Yes

Power-down (3)

VIL X (1) X (1) X (1) X (1) X (1)

X (1)

Hi-Z

Hi-Z

IPD

No

Note: 1. X = VIH or VIL.

2. Output Disable mode should not be kept longer than 1µs.

3. Power-down mode can be entered from Stand-by state, and all DQ pins are in Hi-Z state.

4. Can be either VIL or VIH but must be valid before Read or Write.

5. Byte Read is not supported.

6. Either or both LB and UB must be Low, VIL, for Read operations.

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