M69AR048B データシートの表示（PDF） - STMicroelectronics
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M69AR048B Datasheet PDF : 29 Pages
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M69AR048B
SUMMARY DESCRIPTION
The M69AR048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 1.65V to 1.95V
supply voltage range.
M69AR048B is a member of STMicroelectronics
1T/1C (one transistor per cell) memory family.
These devices are manufactured using dynamic
random access memory cells, to minimize the cell
size, and maximize the amount of memory that
can be implemented in a given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AR048B han-
dles the periodic refresh cycle, automatically, and
without user involvement.
Write cycles can be performed on a single Byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip Enable (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features several Power-Down modes,
making of power saving a user configurable op-
tion:
■ Partial Power-Down (4 Mbits, 8 Mbits or 16
Mbits) performs a limited refresh of the part of
the PSRAM array that contains essential data.
■ Deep Power-Down achieves a very low
current consumption by halting all the internal
activities. Since the refresh circuitry is halted,
the duration of the power-down should be less
than the maximum period for refresh.
Figure 2. Logic Diagram
VCC
21
A0-A20
16
DQ0-DQ15
W
E1
E2
M69AR048B
G
UB
LB
Table 1. Signal Names
A0-A20
Address Input
DQ0-DQ15 Data Input/Output
E1, E2
Chip Enable, Power-Down
G
Output Enable
W
Write Enable
UB
Upper Byte Enable
LB
Lower Byte Enable
VCC
Supply Voltage
VSS
Ground
NC
Not Connected
(no internal connection)
VSS
AI08154
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