M69KB096AA データシートの表示（PDF） - STMicroelectronics

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M69KB096AA

64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM

STMicroelectronics 

M69KB096AA

Deep Power-Down Mode. Deep power-down

(DPD) mode is used by the system memory con-

troller to de-activate the PSRAM device when its

storage capabilities are not needed. All refresh-re-

lated operations are then disabled. When the

Deep Power-Down mode is enabled, the data

stored in the device become corrupted. When re-

Figure 4. Synchronous Burst Read Mode

K

A0-A21

Address

Valid

fresh operations have been re-enabled, the device

will be available for normal operations after tVCHEL

(time to perform an initialization sequence). During

this delay, the current consumption will be higher

than the specified standby levels, but considerably

lower than the active current.

ADV

E

Latency Code 2 (3 clocks)

G

W

Hi Z

Hi Z

WAIT

DQ0-DQ15

DQ0

DQ1

DQ2

DQ3

LB/UB

Burst Read Identified

(W = High)

AI06774b

Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

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