M69KB096AA データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M69KB096AA

64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM

STMicroelectronics 

Figure 5. Synchronous Burst Write Mode (4-word burst)

K

A0-A21

Address

Valid

L

M69KB096AA

E

G

W

LB/UB

Hi Z

Hi Z

WAIT

DQ0-DQ15

DQ0

DQ1 DQ2

DQ3

Additional WAIT states inserted

to allow Refresh completion

AI06776c

Note: Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

Figure 6. Collision Between Refresh and Read Operation

K

A0-A21

Address

Valid

L

E

G

W

LB/UB

Hi Z

Hi Z

WAIT

DQ0-DQ15

DQ0

DQ1 DQ2

DQ3

Additional WAIT states inserted

to allow Refresh completion

AI06776b

Note: Additional Wait states inserted to allow Refresh completion.

Non-default BCR Register settings: 3 clock cycle latency; WAIT active Low; Hold Data one clock; WAIT asserted during delay.

11/48

Share Link: