M69KB096AA データシートの表示（PDF） - STMicroelectronics

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M69KB096AA

64 Mbit (4M x16) 1.8V Supply, 80MHz Clock Rate, Burst PSRAM

STMicroelectronics 

M69KB096AA

SIGNAL DESCRIPTIONS

The signals are summarized in Figure 2., Logic Di-

agram, and Table 1., Signal Names.

Address Inputs (A0-A21). The Address Inputs

select the cells in the memory array to access dur-

ing Read and Write operations.

Data Inputs/Outputs (DQ8-DQ15). The Upper

Byte Data Inputs/Outputs carry the data to or from

the upper part of the selected address during a

Write or Read operation, when Upper Byte Enable

(UB) is driven Low. When disabled, the Data In-

puts/Outputs are high impedance.

Data Inputs/Outputs (DQ0-DQ7). The Lower

Byte Data Inputs/Outputs carry the data to or from

the lower part of the selected address during a

Write or Read operation, when Lower Byte Enable

(LB) is driven Low.

Chip Enable (E). Chip Enable, E, activates the

device when driven Low (asserted). When deas-

serted (VIH), the device is disabled and goes auto-

matically in low-power Standby mode or Deep

Power-down mode.

Output Enable (G). Output Enable, G, provides a

high speed tri-state control, allowing fast read/

write cycles to be achieved with the common I/O

data bus.

Write Enable (W). Write Enable, W, controls the

Bus Write operation of the memory. When assert-

ed (VIL), the device is in Write mode and Write op-

erations can be performed either to the

configuration registers or to the memory array.

Upper Byte Enable (UB). The Upper Byte En-

able, UB, gates the data on the Upper Byte Data

Inputs/Outputs (DQ8-DQ15) to or from the upper

part of the selected address during a Write or

Read operation.

Lower Byte Enable (LB). The Lower Byte En-

able, LB, gates the data on the Lower Byte Data

Inputs/Outputs (DQ0-DQ7) to or from the lower

part of the selected address during a Write or

Read operation.

If both LB and UB are disabled (High) during an

operation, the device will disable the data bus from

receiving or transmitting data. Although the device

will seem to be deselected, it remains in an active

mode as long as E remains Low.

Clock Input (K). The Clock, K, is an input signal

to synchronize the memory to the microcontroller

or system bus frequency during Synchronous

Burst Read and Write operations.

The Clock input is required during all synchronous

operations, except in Standby and Deep Power-

Down. It must be kept Low during asynchronous

operations.

Configuration Register Enable (CR). When this

signal is driven High, VIH, Write operations load ei-

ther the value of the Refresh Configuration Regis-

ter (RCR) or the Bus configuration register (BCR).

Latch Enable (L). The Latch Enable input is

used to latch the address. Once the first address

has been latched, the state of L controls whether

subsequent addresses come from the address

lines (L = VIL) or from the internal Burst counter (L

= VIH).

The Latch Enable signal, L, must be held Low, VIL,

during Asynchronous operations.

Wait (WAIT). The WAIT output signal provides

data-valid feedback during Synchronous Burst

Read and Write operations. The signal is gated by

E. Driving E High while WAIT is asserted may

cause data corruption.

Once a Read or Write operation has been initiated,

the WAIT signal goes active to indicate that the

M69KB096AA device requires additional time be-

fore data can be transferred.

The WAIT signal also is used for arbitration when

a Read or Write operation is launched while an on-

chip refresh is in progress (see Figure 6., Collision

Between Refresh and Read Operation and Figure

7., Collision between Refresh and Write Opera-

tion).

The WAIT signal on the M69KB096AA device is

typically connected to a shared system-level WAIT

signal. The shared WAIT signal is used by the pro-

cessor to coordinate transactions with multiple

memories on the synchronous bus.

See the Operating Modes section for details on the

WAIT signal operation.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Write,

etc.) and for driving the refresh logic, even when

the device is not being accessed.

VCCQ Supply Voltage. VCCQ provides the power

supply for the I/O pins. This allows all Outputs to

be powered independently from the core power

supply, VCC.

VSS Ground. The VSS Ground is the reference for

all voltage measurements.

VSSQ Ground. VSSQ ground is the reference for

the input/output circuitry driven by VCCQ. VSSQ

must be connected to VSS.

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