M69KB096AA データシートの表示（PDF） - STMicroelectronics
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M69KB096AA Datasheet PDF : 48 Pages
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M69KB096AA
Table 2. Bus Modes– Asynchronous Mode
MODE
POWER K
L
E
G
Asynchronous Active >
Read
Standby
L
L
L
L
Asynchronous Active >
Write
Standby
L
L
L
X
Standby
Standby L
X
H
X
Write
Configuration Active
L
L
L
H
Register
Deep Power-
Down (DPD)
Deep
Power-
Down
L
X
H
X
W
CR LB, UB WAIT DQ15-DQ0 NOTES
(2)
(1)
H
L
L1 Low Z Data-Out
3
L
L
L1 Low Z Data-In
3
X
L
X High Z High-Z
4,5
L
H
X Low Z High-Z
X
X
X High-Z High-Z
6
Table 3. Bus Modes– Synchronous Burst Mode
MODE
POWER K
L
E
G
W CR LB, UB WAIT DQ15-DQ0 NOTES
(2)
(1)
Initial Burst
Read
Active >
Standby
!
L
L
X
H
L
L
Low Z Data-Out 3, 7, 8
Initial Burst Active > !
Write
Standby
L
L
H
L
L
X Low Z Data-In 3, 7, 8
Subsequent
Burst
Operation
Active >
Standby
!
H
L
X
X
X
L
Low Z
Data-In or
Data-Out
3, 7, 8
Burst
Suspend
Active >
Standby
X(9)
X
L
H
X
L
X Low Z High-Z
3, 7
Write
Configuration Active
!
L
L
H
L
H
X Low Z High-Z
7, 8
Register
Deep Power-
Down (DPD)
Deep
Power-
Down
L
X
H
X
X
X
X High-Z High-Z
6
Note: 1. When LB and UB are in select mode (Low), DQ15-DQ0 are affected. When only LB is in select mode, DQ7-DQ0 are affected. When
only UB is in the select mode, DQ15-DQ8 are affected.
2. The WAIT polarity is configured through the Bus Configuration Register (BCR10).
3. The device consumes active power in this mode whenever addresses are changed.
4. When the device is in Standby mode, Address inputs and Data inputs/outputs are internally isolated from any external influence.
5. VIN = VCC or 0V.
6. The device remains in Deep Power-Down mode until the RCR register is reconfigured.
7. The Synchronous Burst mode is initialized through the Bus Configuration Register (BCR15).
8. The clock polarity is configured through the Bus Configuration Register (BCR6).
9. The Clock signal, K, must remain stable during Burst Suspend operations.
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