M69KB096AA データシートの表示（PDF） - STMicroelectronics
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M69KB096AA Datasheet PDF : 48 Pages
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M69KB096AA
OPERATING MODES
The M69KB096AA supports Asynchronous Ran-
dom Read, Page Read and Synchronous Burst
Read and Write modes.
The device mode is defined by the value that has
been loaded into the Bus Configuration Register.
The Page mode is controlled by the Refresh Con-
figuration Register (RCR7).
Power-Up
PSRAM devices include an on-chip voltage sen-
sor used to launch the power-up sequence. VCC
and VCCQ must be applied simultaneously. Once
they reach a stable level, equal to or higher than
1.70V, the device will require tVCHEL to complete
its self-initialization process. During the initializa-
tion period, the E signal should remain High. Once
initialization has completed, the device is ready for
normal operation. Initialization will configure the
Bus Configuration Register (BCR) and the Refresh
Configuration Register (RCR) with their default
settings (see Table 5., page 16, and Table
9., Refresh Configuration Register Definition).
See Figure 34., Power-Up AC Waveforms and Ta-
ble 19., Power-Up AC Characteristics, for details
on the Power-up timing.
Asynchronous Random Read and Write Modes
At power-up, the device is in Asynchronous Ran-
dom Read mode. This mode uses the industry
standard control bus (E, G, W, LB, UB). Read op-
erations are initiated by bringing E, G, and LB, UB
Low, VIL, while keeping W High, VIH. Valid data will
be gated through the output buffers after the spe-
cific access time tAVQV has elapsed.
The WAIT signal will remain active until valid data
is output from the device and its state should be ig-
nored.
Write operations occur when E, W, LB and UB are
driven Low. During Asynchronous Random Write
operations, the G signal is “don't care” and W will
override G. The data to be written is latched on the
rising edge of E, W, LB or UB (whichever occurs
first). During Write operations, the WAIT signal in-
dicates to the system memory controller that data
have been programmed into the memory.
During asynchronous operations (Page mode dis-
abled), the L input can either be used to latch the
address or kept Low, VIL, during the entire Read/
Write operation. The Clock input signal K must be
held Low, VIL.
See Figures 15, 16 and Table 15. for details of
Asynchronous Read AC timing requirements.
See Figures 23, 24, 25, 26, and Table 17. for de-
tails of Asynchronous Write AC timing require-
ments.
Asynchronous Page Read Mode
The Asynchronous Page read mode gives greater
performance, even than the traditional Asynchro-
nous Random Read mode. The page mode is not
available for write operations.
Asynchronous Page Read mode is enabled by
setting RCR7 to ‘1’. L must be driven Low, VIL, dur-
ing all Asynchronous Page Read operations.
In Asynchronous Page Read mode, a Page of
data is internally read. Each memory page con-
sists of 16 Words, and has the same set of values
on A4-A21; only of A0 to A3 differ. The first read
operation within the Page has the normal access
time (tAVQV), subsequent reads within the same
Page have much shorter access times (tAVQV1). If
the Page changes then the normal, longer timings
apply again.
During Asynchronous Page Read mode, the K in-
put must be held Low, VIL. E must be kept Low, VIL
upon completion of an Asynchronous Page Read
operation. The WAIT signal remains active until
valid data is output from the device.
See Figure 17. and Table 15. for details of the
Asynchronous Page Read timing requirements.
Synchronous Burst Mode
Burst mode allows high-speed synchronous read
and write operations.
In Synchronous Burst mode, the data is input or
output to or from the memory array in bursts that
are synchronized with the clock. After E goes Low,
the data address is latched on the first rising edge
of the Clock, K. During this first clock rising edge,
the W signal indicates whether the operation is go-
ing to be a Read (W=VIH, Figure 4.) or Write
(W=VIL, Figure 5.).
In Synchronous Burst mode, the number of Words
to be input or output during a Synchronous Burst
operation can be configured in the Bus Configura-
tion Register, BCR, as fixed length (4 Words, 8
Words or 16 Words) or Continuous. In Synchro-
nous Continuous Burst mode, the entire memory
can be accessed sequentially in one Burst opera-
tion.
The Latency Counter, stored in the BCR11 to
BCR13 bits of the BCR register, defines how many
clock cycles elapse before the first data value is
transferred between the processor and the
M69KB096AA.
The WAIT output will be asserted as soon as a
Synchronous Burst operation is initiated and will
be deasserted to indicate when data is to be trans-
ferred into (or out of) the memory array. The WAIT
signal is also asserted when a Continuous Burst
Read or Write operation crosses a row boundary.
The WAIT assertion allows time for the new row to
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