MAX1586C データシートの表示（PDF） - Maxim Integrated

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MAX1586C

High-Efficiency, Low-IQ PMICs with Dynamic Core for PDAs and Smart Phones

Maxim Integrated 

High-Efficiency, Low-IQ PMICs with

Dynamic Core for PDAs and Smart Phones

ELECTRICAL CHARACTERISTICS (continued)

(VIN = 3.6V, VBKBT = 3.0V, VLBI = 1.1V, VDBI = 1.35V, circuit of Figure 5, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)

PARAMETER

CONDITIONS

MIN

MAX UNITS

DBI Threshold (Falling)

MAX1586,

hysteresis is 5% (typ)

DBI = IN (for preset)

With resistors at LBI

2.993

1.208

3.307

V

1.256

RSO Threshold (Falling)

Voltage on REG7, hysteresis is 5% (typ)

2.25

2.60

V

RSO Deassert Delay

62

69

ms

LBI Input Bias Current

MAX1586

-50

nA

DBI Input Bias Current

MAX1586

75

nA

LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output

Low Level

2.6V ≤ V7 ≤ 5.5V, sinking 1mA

0.4

V

LBO, DBO, POK, RSO, SDA Output

Low Level

V7 = 1V, sinking 100µA

0.4

V

LBO, DBO, POK, RSO Output-High

Leakage Current

Pin = 5.5V

0.2

µA

ON_, SCL, SDA, SLP, PWM3, MR,

SRAD Input High Level

2.6V ≤ VIN ≤ 5.5V

1.6

V

ON_, SCL, SDA, SLP, PWM3, MR,

SRAD Input Low Level

2.6V ≤ VIN ≤ 5.5V

0.4

V

ON_, SCL, SDA, SLP, PWM3, MR,

SRAD Input Leakage Current

Pin = GND, 5.5V

-1

+1

µA

SERIAL INTERFACE

Clock Frequency

400 kHz

Bus-Free Time Between START and

STOP

1.3

µs

Hold Time Repeated START

Condition

0.6

µs

CLK Low Period

CLK High Period

1.3

µs

0.6

µs

Setup Time Repeated START

Condition

0.6

µs

DATA Hold Time

DATA Setup Time

Setup Time for STOP Condition

0

µs

100

ns

0.6

µs

8 _______________________________________________________________________________________

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